DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The examiner proposes QUANTUM TRANSISTORS WITH NONLINEAR ARRANGEMENT OF PLUNGER AND BARRIER GATES
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5 and 18-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 5 recites “the fourth straight axis S4”, which lacks antecedent basis. For present purposes the examiner will assume that this is the same as the “fourth straight axis” recited in claim 3.
Claim 18 recites “[a] manufacturing method for a semiconductor device, further comprising ….” This is the preamble of an independent claim, so it is not clear what “further” means here.
Claims 19 and 20 are rejected based on their dependencies.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Clarke, US 2019/0252377 A1.
Claim 1: Clarke discloses:
a substrate;
“the layers of the quantum well stacks 146 may be grown on a substrate (e.g., a silicon or germanium wafer)” [0063].
and a quantum dot transistor (100) disposed on the substrate and comprising:
a first barrier gate stack (150, FIG. 3);
a second barrier gate stack (150);
and a first plunger gate stack (160) disposed between the first barrier gate stack and the second barrier gate stack;
wherein the first barrier gate stack and the first plunger gate stack are arranged in a first straight axis, the first plunger gate stack and the second barrier gate stack are arranged in a second straight axis, and there is a first angle between the first straight axis and the second straight axis is not equal to 180° (FIG. 3).
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Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Leipold, US 2024/0113240 A1.
Claim 1: Leipold discloses
a substrate;
and a quantum dot transistor disposed on the substrate and comprising:
a first barrier gate stack (196, FIG. 12; 174, portion between 32 and 31, FIG. 11);
a second barrier gate stack (174, portion between 32 and 33);
and a first plunger gate stack (172 (#32), FIG. 11; 184, FIG. 12) disposed between the first barrier gate stack and the second barrier gate stack;
wherein the first barrier gate stack and the first plunger gate stack are arranged in a first straight axis, the first plunger gate stack and the second barrier gate stack are arranged in a second straight axis, and there is a first angle between the first straight axis and the second straight axis is not equal to 180° (FIG. 11).
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Claim 1 is rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Li, US 2023/0389346 A1.
Claim 1: Li discloses
a substrate (10);
and a quantum dot transistor disposed on the substrate and comprising:
a first barrier gate stack (135);
a second barrier gate stack (137);
and a first plunger gate stack (127) disposed between the first barrier gate stack and the second barrier gate stack;
wherein the first barrier gate stack and the first plunger gate stack are arranged in a first straight axis, the first plunger gate stack and the second barrier gate stack are arranged in a second straight axis, and there is a first angle between the first straight axis and the second straight axis is not equal to 180° (FIG. 12B).
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Claims 1-4 and 13-20 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Pillarisetty, US 2020/0321436 A1.
Claim 1: Pillarisetty discloses
a substrate;
“quantum dot devices as described herein may be provided over any substrate” [0027]
and a quantum dot transistor disposed on the substrate and comprising:
a first barrier gate stack (160);
a second barrier gate stack (160);
and a first plunger gate stack (150) disposed between the first barrier gate stack and the second barrier gate stack;
wherein the first barrier gate stack and the first plunger gate stack are arranged in a first straight axis, the first plunger gate stack and the second barrier gate stack are arranged in a second straight axis, and there is a first angle between the first straight axis and the second straight axis is not equal to 180° (FIG. 3).
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Claim 2: the quantum dot transistor further comprises:
a second plunger gate stack;
and a third barrier gate stack;
wherein the second plunger gate stack is disposed between the second barrier and the third barrier gate stack, the second plunger gate stack and the third barrier gate stack are arranged in a third straight axis, and there is a second angle between the second straight axis and the third straight axis is not equal to 180°.
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Claim 3: the quantum dot transistor further comprises:
a second plunger gate stack;
and a fourth barrier gate stack;
wherein the second plunger gate stack is disposed between the second barrier and the fourth barrier gate stack, the second plunger gate stack and the fourth barrier gate stack are arranged in a fourth straight axis, and there is a third angle between the second straight axis and the fourth straight axis is not equal to 180°.
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Claim 4: the third angle is 60°.
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Claim 13: Pillarisetty discloses
a substrate;
“quantum dot devices as described herein may be provided over any substrate” [0027]
and a quantum dot transistor disposed on the substrate and comprising:
a plurality of barrier gate (160) stacks;
and a plurality of plunger gate (150) stacks;
wherein the barrier gate stacks and the plunger gate stacks are arranged in a line, and the line is composed of a straight axis, a curved axis or a combination thereof (FIG. 1).
Claim 14: the line is a polygonal shape (FIG. 1A).
Claim 15: the line is a circular shape (FIG. 1A).
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Claim 16: the line is an elliptical shape (FIG. 3B).
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Claim 17: the semiconductor device comprises a plurality of the quantum dot transistors (cells 170), and the quantum dot transistors share one or some of the barrier gate stacks and one or some of the plunger gate stacks (FIG. 1A).
Claim 18: Pillarisetty discloses
providing a substrate;
“quantum dot devices as described herein may be provided over any substrate” [0027]
and forming a quantum dot transistor on the substrate, wherein the quantum dot transistor comprises a plurality of barrier gate stacks (160) and a plurality of plunger gate stacks (150),
wherein the barrier gate stacks and the plunger gate stacks are arranged in a line, and the line is composed of a straight axis, a curved axis or a combination thereof (FIG. 1A).
Claim 19 in forming the quantum dot transistor on the substrate, the barrier gate stacks and the plunger gate stacks are arranged in a polygonal shape (FIG. 1A).
Claim 20: in forming the quantum dot transistor on the substrate, a plurality of the quantum dot transistors (cells 170), share one or some of the barrier gate stacks and one or some of the plunger gate stacks (FIG. 1A).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5-12 are rejected under 35 U.S.C. 103 as being unpatentable over Pillarisetty in view of Gorman, US 2024/0420004 A1, or vice versa. Pillarisetty discloses a hexagonal arrangement with three quantum dots (FIGS. 1A and 1B). However, it was known in the art to have a hexagonal arrangement with six quantum dots (306, FIG. 3). It would have been obvious to have this arrangement as known in the art, particularly as it was known to have various different configurations of quantum dots in a transistor (e.g. Gorman FIG. 3). Alternatively, Gorman discloses barriers between the quantum dots that can allow for tunneling (see t, FIG. 2, [0055]). These can fall within the broadest reasonable interpretation of barrier gate, or it would have been obvious to have used a barrier gate such as Pillarisetty discloses as known to control the tunneling of the barrier height and thus the tunneling.
Claim 5: Gorman (combined with Pillarisetty) discloses that the quantum dot transistor further comprises:
a third plunger gate stack;
and a fifth barrier gate stack;
wherein the third plunger gate stack is disposed between the fourth barrier gate stack and the fifth barrier gate stack, the third plunger gate stack and the fifth barrier gate stack are arranged in a fifth straight axis, and there is a fourth angle between the fourth straight axis S4 and the fifth straight axis is not equal to 180°.
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Claim 6: the fourth angle is 60°.
Claim 7: the quantum dot transistor further comprises:
a fourth plunger gate stack;
and a sixth barrier gate stack;
wherein the fourth plunger gate stack is disposed between the fifth barrier gate stack and the sixth barrier gate stack, the fourth plunger gate stack and the sixth barrier gate stack are arranged in a sixth straight axis, and there is a fifth angle between the fifth straight axis and the sixth straight axis is not equal to 180°.
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Claim 8: the fifth angle is 60°.
Claim 9: the quantum dot transistor further comprises: a fifth plunger gate stack; and a seventh barrier gate stack; wherein the fifth plunger gate stack is disposed between the sixth barrier gate stack and the seventh barrier gate stack, the fifth plunger gate stack and the seventh barrier gate stack are arranged in a seventh straight axis, and there is a sixth angle between the sixth straight axis and the seventh straight axis is not equal to 180°.
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Claim 10: the sixth angle is 60°.
Claim 11: the quantum dot transistor further comprises: a sixth plunger gate stack; and an eighth barrier gate stack; wherein the sixth plunger gate stack is disposed between the seventh barrier gate stack and the eighth barrier gate stack, the sixth plunger gate stack and the eighth barrier gate stack are arranged in an eighth straight axis, and there is a seventh angle between the seventh straight axis and the eighth straight axis is not equal to 180°.
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Claim 12: the seventh angle is 60°.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER BRADFORD whose telephone number is (571)270-1596. The examiner can normally be reached 10:30-6:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469.295.9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PETER BRADFORD/Primary Examiner, Art Unit 2897
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