CTNF 18/672,951 CTNF 90001 DETAILED ACTION Examiner’s Note Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182. Examiner has cited particular paragraphs, columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. See MPEP 2141.02 VI. In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 1-5 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Koester et al. (US 20110233785 A1, hereinafter Koester’785) . Regarding independent claim 1 , Koester’785 teaches, “A semiconductor die (fig. 1-25; ¶ [0025] - ¶ [0086]) comprising: a substrate (2, fig. 9) having a frontside (facing element 4) opposing a backside (facing dielectric layer 90); a device layer (32) disposed over the frontside of the substrate (2); interconnect layers (40) formed over the device layer (32); and at least one dummy feature (70), the at least one dummy feature (70) extending from the backside of the substrate (2) through a portion of the substrate (2), wherein the dummy feature comprises one or more metal layers (¶ [0044])”. Regarding claim 2 , Koester’785 further teaches, “The semiconductor die of claim 1, further comprising at least one metal pad (62, fig. 9) disposed over a surface on the frontside of the substrate (2), wherein the at least one metal pad (62) is aligned in a first direction with each of the at least one dummy features (70), and the first direction is parallel to the surface”. Regarding claim 3 , Koester’785 further teaches, “The semiconductor die of claim 1, further comprising at least one metal pad (92, fig. 9) disposed over the backside of the substrate (2) and over each of the at least one dummy features (70)”. Regarding claim 4 , Koester’785 further teaches, “The semiconductor die of claim 1, further comprising at least one working TSV (50, fig. 9), wherein the at least one working TSV extends from the backside of the substrate to an interconnect feature (62) disposed within the interconnect layers”. Regarding claim 5 , Koester’785 further teaches, “The semiconductor die of claim 4, wherein the at least one working TSV (50, fig. 9) has a larger width than the at least one dummy feature (70)” . Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-21-aia AIA Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Koester’785 in view of Nguyen et al. (US 20050014361 A1, hereinafter Nguyen’361) . Regarding independent claim 6 , Koester’785 teaches, “A method (fig. 1-25; ¶ [0025] - ¶ [0086]) comprising: ((depositing a photoresist layer on a backside of a substrate,)) the substrate (2, fig. 7) comprising a device layer (32) disposed on a frontside (facing element 110) of the substrate, and interconnect layers (40) disposed over the device layer (32); ((patterning the photoresist layer to form first patterned features that expose portions of the backside of the substrate, the first patterned features having a first critical dimension;)) etching the portions of the backside of the substrate (2, fig. 7) exposed by the first patterned features using a first etching process to form first features (69), the first features extending from the backside of the substrate (2) through a portion of the substrate (2); and filling the first features (69) with a metal to form dummy features (70)”. But Koester’785 is silent upon the provision of wherein the method comprising steps of: depositing a photoresist layer on a backside of a substrate, patterning the photoresist layer to form first patterned features that expose portions of the backside of the substrate, the first patterned features having a first critical dimension; However, Nguyen’361 teaches a similar process of forming vias in a substrate using conventional photolithography with below steps: depositing a photoresist layer (314, ‘resist material’, fig. 3A; ¶ [0070]) on a backside of a substrate (312), patterning the photoresist layer (314, ‘The resist material 314 is then pattern etched to define via openings 313’, ¶ [0070]) to form first patterned features (313) that expose portions of the backside of the substrate (312), the first patterned features (313) having a first critical dimension; It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Koester’785 and Nguyen’361 to use photoresist to form vias according to the teachings of Nguyen’361 as this is conventional in the related field . 07-22-aia AIA Claim s 7-19 are rejected under 35 U.S.C. 103 as being unpatentable over Koester’785 and Nguyen’361 as applied to claim 6 as above, and further in view of Park (US 20110215457 A1, hereinafter Park’457) . Regarding claim 7 , Koester’785 modified with Nguyen’361 teaches all the limitations described in claim 6. Koester’785 further teaches, wherein filling the first features comprises: depositing a barrier layer (71, fig. 8) in the first features (69), the barrier layer lining sidewalls and a bottom surface of the first features (69); ((depositing a seed layer over the barrier layer; and)) filling the first features (69) with a metal fill material (70); and planarizing the first features using a CMP process (¶ [0045])”. But Koester’785 modified with Nguyen’361 is silent upon the provision of wherein filling the first features comprises: depositing a seed layer over the barrier layer; However, Park’457 teaches a similar process, wherein TSV structures may be formed with one or more layers or suitable conductive material (e.g. copper), such as by chemical vapor deposition (CVD), sputtering, physical vapor deposition (PVD), electro-plating, electro-less plating, or the like (¶ [0019]). It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Koester’785 modified with Nguyen’361 and Park’457 to include seed/multiple layers in a TSV according to the teachings of Park’457 as this is a conventional feature in the related field. Regarding claim 8 , Koester’785 modified with Nguyen’361 and Park’457 further teaches, “The method of claim 6, further comprising patterning the photoresist layer to form second patterned features that expose portions of the backside of the substrate, the second patterned features are aligned with conductive features formed in the interconnect layers and have a second critical dimension different from the first critical dimension (Park’457, fig. 1; ¶ [0019], claim 15, dummy TSV openings (133-138) are smaller in size than the active or regular TSV openings (131-132))”. Regarding claim 9 , Koester’785 modified with Nguyen’361 and Park’457 further teaches, “The method of claim 8, wherein the second critical dimension is greater than the first critical dimension (Park’457, fig. 1; ¶ [0019], claim 15, dummy TSV openings (133-138) are smaller in size than the active or regular TSV openings (131-132))”. Regarding claim 10 , Koester’785 modified with Nguyen’361 and Park’457 further teaches, “The method of claim 8, further comprising etching second features through the portions of the backside of the substrate exposed by the second patterned features, the second features extending from the backside of the substrate to a corresponding conductive feature (Park’457, fig. 1; ¶ [0019], claim 15)”. Regarding claim 11 , Koester’785 modified with Nguyen’361 and Park’457 further teaches, “The method of claim 10, wherein the etching second features is performed etched during the first etching process or is performed using a second etching process performed after the first etching process and prior to filling the first features (Park’457, fig. 1; ¶ [0019], claim 15)”. Regarding claim 12 , Koester’785 modified with Nguyen’361 and Park’457 further teaches, “The method of claim 11, further comprising filling the second features (50, fig. 7, Koester’785) with a metal to form working TSVs”. Regarding claim 13 , Koester’785 modified with Nguyen’361 and Park’457 further teaches, “The method of claim 6, further comprising forming metal pads (C4/98, fig. 9, Koester’785) over the first features (69/70) after filling the first features with a metal”. Regarding claim 14 , Koester’785 modified with Nguyen’361 and Park’457 further teaches, “The method of claim 13, wherein forming the metal pads (C4/98, fig. 9; ¶ [0049] -¶ [0050], Koester’785) over the first features comprises: forming a patterned mask layer over the backside of the substrate that exposes the first features; and depositing a conductive material over the exposed first features”. Regarding claim 15 , Koester’785 modified with Nguyen’361 and Park’457 further teaches, “The method of claim 6, wherein the substrate (2, fig. 6, Koester’785) comprises second features (51) that are aligned with a corresponding conductive feature (62, 162) and extend from the backside of the substrate (2) to a corresponding conductive feature prior to the depositing of the photoresist layer (fig. 7) on the backside of a substrate”. Regarding claim 16 , Koester’785 modified with Nguyen’361 and Park’457 further teaches, “The method of claim 15, further comprising filling the second features (50, fig. 2, Koester’785) to form working TSVs”. Regarding claim 17 , Koester’785 modified with Nguyen’361 and Park’457 further teaches, “The method of claim 6, wherein the substrate (2, fig. 9, Koester’785) comprises dummy trenches (69) that are aligned with a corresponding conductive feature and extend from the backside of the substrate (2) to a dummy depth measured from the frontside of the substrate”. Regarding claim 18 , Koester’785 modified with Nguyen’361 and Park’457 further teaches, “The method of claim 17, wherein the dummy depth is equal to a thickness of the substrate and a depth of the first features (fig. 9; ¶ [0046], Koester’785)”. Regarding claim 19 , Koester’785 modified with Nguyen’361 and Park’457 further teaches, “The method of claim 18, further comprising: patterning the photoresist layer to form second patterned features that expose portions of the backside of the substrate, the second patterned features are aligned with the dummy trenches and have a second critical dimension different from the first critical dimension; etching the portions of the backside of the substrate between the dummy trenches and the backside of the substrate to form second features; and filling the first features and the second features (Park’457, fig. 1, ¶ [0019], claim 15)” . 07-21-aia AIA Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Koester’785 in view of Park’457 . Regarding independent claim 20 , Koester’785 teaches, “A stacked semiconductor assembly (fig. 1-25; ¶ [0025] - ¶ [0086]) comprising: ((a second level of semiconductor dies disposed above a first level of semiconductor dies)), each of the semiconductor dies comprising: a substrate (2, fig. 9) having a frontside (facing element 4) opposing a backside (facing dielectric layer 90); a device layer (32) disposed over the frontside of the substrate (2); interconnect layers (40) formed over the device layer (32), the interconnect layers (40) having interconnect features formed therein; at least one dummy feature (70), the at least one dummy feature (70) extending from the backside of the substrate (2) through a portion of the substrate (2), wherein the dummy feature (70) comprises a metal; and at least one working TSV (50) extending from the backside of the substrate (2) to a corresponding interconnect feature (42), ((wherein each of the at least one working TSV of each of the semiconductor dies of second level of semiconductor dies is aligned with a corresponding working TSV of the at least one working TSV of each of the semiconductor dies of first level of semiconductor dies))”. But Koester’785 is silent upon the provision of wherein a second level of semiconductor dies disposed above a first level of semiconductor dies, each of the semiconductor dies comprising: wherein each of the at least one working TSV of each of the semiconductor dies of second level of semiconductor dies is aligned with a corresponding working TSV of the at least one working TSV of each of the semiconductor dies of first level of semiconductor dies”. However, Park’457 teaches a similar device (claim 17), a second side of a second wafer substrate is bonded to a first side of a first wafer substrate such that each of first set of conductive through-silicon via structures in the second wafer substrate is aligned to contact a corresponding first conductive through-silicon via structure in the first wafer substrate. Koester’785 and Park’457 are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Koester’785 with the features of Park’457 because they are from the same field of endeavor. It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Koester’785 and Park’457 to include multiple levels of dies (wafers) according to the teachings of Park’457 with a general motivation of stacking wafers to reduce horizontal footprint, reduce resistance, reduce parasitic capacitance etc. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD M HOQUE whose telephone number is (571)272-6266 and email address is mohammad.hoque@uspto.gov. The examiner can normally be reached 9AM-7PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached on (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MOHAMMAD M HOQUE/Primary Examiner, Art Unit 2817 Application/Control Number: 18/672,951 Page 2 Art Unit: 2817 Application/Control Number: 18/672,951 Page 3 Art Unit: 2817 Application/Control Number: 18/672,951 Page 4 Art Unit: 2817 Application/Control Number: 18/672,951 Page 5 Art Unit: 2817 Application/Control Number: 18/672,951 Page 6 Art Unit: 2817 Application/Control Number: 18/672,951 Page 7 Art Unit: 2817 Application/Control Number: 18/672,951 Page 8 Art Unit: 2817 Application/Control Number: 18/672,951 Page 9 Art Unit: 2817 Application/Control Number: 18/672,951 Page 10 Art Unit: 2817 Application/Control Number: 18/672,951 Page 11 Art Unit: 2817 Application/Control Number: 18/672,951 Page 12 Art Unit: 2817
Prosecution Insights