DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 05/24/24 & 03/14/25 was/were received by the Examiner before the issuance/mailing date of the first office action. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) has/have been considered (except for anything in foreign language non-accompanied by an English translation) by the Examiner.
Claim Objections
Claims 4-5 and 12-13 are objected to because of the following informalities: claims 4 and 10 each should recite “are overlapped” instead of “is overlapped”. Claims 5 and 13 should recite (each in two instances) “aligns with” instead of “aligns” because the first side or second side does not perform the action of aligning something but are merely aligned with something. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 9 and 18 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claim 9 recites “and a second surface device, disposed over the substrate and within the ring structure in the vertical projection, the second surface device being electrically coupled to the semiconductor die through the substrate, wherein the second surface device and the semiconductor die are disposed on opposite surfaces of the substrate along the stacking direction.” (emphasis added). There is apparently no support for the underlined limitation because it means that the semiconductor die is on the top surface of the substrate while the second surface device is on the bottom surface of said substrate while being a ring structure that is on the top surface. There is no support for this in the original disclosure. The same remarks apply to claim 18 that recites “mounting second surface device on the substrate and within the ring structure in the vertical projection, the second surface device being electrically coupled to the semiconductor die through the substrate, wherein the second surface device and the semiconductor die are disposed on opposite surfaces of the substrate along the stacking direction”.
Double Patenting
Claims 8 is objected to under 37 CFR 1.75 as being a substantial duplicate of claim 7. When two claims in an application are duplicates or else are so close in content that they both cover the same thing, despite a slight difference in wording, it is proper after allowing one claim to object to the other as being a substantial duplicate of the allowed claim. See MPEP § 608.01(m).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 7-8, 10-12, 15-16, 17 and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Eid et al. (US 2019/0326192).
a. Re claim 1, Eid et al. disclose a package, comprising: a substrate 120 (see fig. 6, [0032]; see remaining of disclosure for more details); a ring structure 142 ([0040], [0048]), disposed over the substrate; a die 1102 (or 1101 in the alternative; see [0032]; it is noted that the last digit of the dies labels are underscored in the drawings but not in the specification, but there is no confusion to have), disposed over the substrate and within the ring structure; and a lid 150, disposed over the substrate, the die being between the substrate and the lid, wherein the lid comprises a first portion P1 (see annotated fig. 6 below) and a second portion P2 surrounding the first portion, the first portion has a first thickness T1 less than a second thickness T2 of the second portion along a stacking direction of the ring structure and the lid (see annotated fig. 6). But Eid et al. do not appear to explicitly disclose that die 1102 is a semiconductor die. However, it is conventionally known in the art to use silicon to make the type of chips (microprocessors, memory, chipsets for example; see [0032]) dies 1101-1103 are representative of. As such, it would have been obvious to one skilled in the art before the effective filing date of the invention to have provided dies 1101-1103 made of silicon, and this as a non-inventive step of using a known material for the type of chips dies 1101-1103 are (see MPEP 2144.07), or simply taking advantage of the low-cost high-integration od silicon to make dies 1101-1103. The modification would have resulted in the package being a semiconductor package, and the die being a semiconductor die.
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b. Re claim 2, the semiconductor die is disposed in a space confined by the substrate, the ring structure, and the lid (explicit on fig. 6).
c. Re claim 3, the semiconductor die (when it is 1101 in the underlined alternative as per claim 1 rejection above) is eccentric with the ring structure in a vertical projection on the substrate along the stacking direction (see fig. 2).
d. Re claim 4, the semiconductor die (when it is 1101 in the underlined alternative as per claim 1 rejection above) and the ring structure are overlapped with the second portion and next to the first portion (explicit on annotated fig. 6).
e. Re claims 7 and 8, semiconductor package of claim 1, further comprising: a surface device 1103, disposed over the substrate and within the ring structure in a vertical projection on the substrate along the stacking direction (see fig. 2), the surface device being electrically coupled to the semiconductor die through the substrate (explicit on fig. 6), wherein the surface device and the semiconductor die are disposed on a same surface of the substrate (explicit on fig. 6).
f. Re claim 10, Eid et al. disclose a semiconductor package, comprising: a substrate 120 (see fig. 6, [0032]; see remaining of disclosure for more details); a semiconductor die 1102 (or 1101 in the alternative; obvious to have been provided as a silicon die as explained in claim 1 rejection above), disposed over the substrate; and an electromagnetic interference shielding structure 140 (i.e. 150&142), disposed over the substrate, wherein the semiconductor die is located in a space confined by the substrate and the electromagnetic interference shielding structure, and wherein the electromagnetic interference shielding structure comprises a frame portion 142 and a block portion 150 over the frame portion, the block portion comprises a first portion P1 and a second portion P2 surrounding the first portion, the first portion has a first T1 thickness less than a second thickness T2 of the second portion along a stacking direction of the substrate and the electromagnetic interference shielding structure.
g. Re claims 11 and 12, see respectively claims 3 and 4 rejections above.
h. Re claim 15, the frame portion is in a form of a full continuous frame annulus in a vertical projection on the substrate along the stacking direction (explicit in view of figs. 2&6, [0040] and [0048]).
i. Re claim 16, the block portion is in a form of a solid block in a vertical projection on the substrate along the stacking direction (explicit in view of figs. 2&6, [0040] and [0048]).
j. Re claim 17, Eid et al. disclose a method of manufacturing a semiconductor package, comprising: providing a semiconductor die 1102 (or 1101 in the alternative; obvious to have been provided as a silicon die as explained in claim 1 rejection above; see fig. 6 and related text as well as remaining of disclosure for more details); mounting the semiconductor die to a substrate 120; adhering a ring structure 142 onto the substrate, the semiconductor die being disposed within the ring structure; and adhering a lid 150 onto the ring structure, the semiconductor die being between the substrate and the lid, wherein the lid comprises a first portion P1 (see annotated fig. 6) and a second portion P2 surrounding the first portion, the first portion has a first thickness T1 less than a second thickness T2 of the second portion along a stacking direction of the ring structure and the lid.
k. Re claim 19, adhering the ring structure onto the substrate comprises adhering the ring structure onto the substrate by a first adhesive 144 ([0040]), adhering the lid onto the ring structure comprises adhering the lid onto the ring structure by a second adhesive 146 ([0048]), and wherein, the ring structure, and the lid constitute an electromagnetic interference shielding structure. But Eid et al. do not appear to explicitly disclose the first and second adhesive being electrically conductive being part (electrically speaking) of the electromagnetic interference shielding structure. However, it is conventionally known in the art to ground lid (or cover) structures by grounding them to ground metallization or pads on a surface of a circuit board using electrically conductive adhesives instead of electrically insulating adhesives. As such, and noting that the rationale to modify or combine the prior art does not have to be expressly stated in the prior art but may be expressly or impliedly contained in the prior art or it may be reasoned from knowledge generally available to one of ordinary skill in the art, established scientific principles, or legal precedent established by prior case law (see MPEP 2144.I), further noting that the desire to enhance commercial opportunities by improving a product or process is universal and even common-sensical (see MPEP 2144.II), and finally noting from MPEP 2141.03 that “A person of ordinary skill in the art is also a person of ordinary creativity, not an automaton” and that a “hypothetical ‘person having ordinary skill in the art’ to which the claimed subject matter pertains would, of necessity have the capability of understanding the scientific and engineering principles applicable to the pertinent art.”, it would have been obvious to one skilled in the art before the effective filing date of the invention to have provided grounding pads or metallization on the top surface of substrate 120 and in the footprint of ring portion 142, and further provided the first and second adhesive layers 144 and 146 to be electrically conductive (by providing them filled with electrically conductive filler particles such as silver particles as known in the art) in order to ground lid structure 140. The modification would have resulted in the first and second adhesive layers being electrically conductive and being part or constituent of the electromagnetic interference shielding structure.
l. Re claim 20, Eid et al. disclose all the limitations of claim 17 except explicitly that the method of claim 17, further comprises: bonding the substrate to a base substrate through a plurality of conductive terminals, the substrate being disposed between and electrically coupled to the base substrate and the semiconductor die. However, wiring substrate 120 is meant to be electrically connected or integrated with other structure as can be seen from the interconnects in dash lines extending through it and away from the dies. It is conventionally known in the art to provide vertical through-vias in wiring substrates in order to interconnect devices mounted above them to other electronic components such as a motherboard mounted (usually via solder balls) below said wiring substrate for integration purpose. As such, and noting that the rationale to modify or combine the prior art does not have to be expressly stated in the prior art but may be expressly or impliedly contained in the prior art or it may be reasoned from knowledge generally available to one of ordinary skill in the art, established scientific principles, or legal precedent established by prior case law (see MPEP 2144.I), further noting that the desire to enhance commercial opportunities by improving a product or process is universal and even common-sensical (see MPEP 2144.II), and finally noting from MPEP 2141.03 that “A person of ordinary skill in the art is also a person of ordinary creativity, not an automaton” and that a “hypothetical ‘person having ordinary skill in the art’ to which the claimed subject matter pertains would, of necessity have the capability of understanding the scientific and engineering principles applicable to the pertinent art.”, it would have been obvious to one skilled in the art before the effective filing date of the invention to have provided the method of claim 17, further comprising: providing through-vias in substrate 120, bonding the substrate to a base substrate (such as a motherboard) through a plurality of conductive terminals (such as conventionally known solder balls), the substrate being disposed between and electrically coupled to the base substrate and the semiconductor die, and this in order to further integrate the dies 1101-1103.
Allowable Subject Matter
Claims 5, 6, 13-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Arvelo et al. (US 2005/0068739) disclose a structure similar to the claimed invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PENIEL M GUMEDZOE whose telephone number is (571)270-3041. The examiner can normally be reached M-F: 9:00AM - 5:30PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 5712707877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PENIEL M GUMEDZOE/Primary Examiner, Art Unit 2899
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