DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 5, 6 and 8-13 are rejected under 35 U.S.C. 102 A1 as being anticipated by Kim-1(US20240038795A1).
Regarding Claim 1, FIG 2 and FIG 4 disclose a method for forming a sensor package, comprising:
providing a sensor (FIG 2 and FIG 4; 200; ¶[0038]);
forming an optical filter (FIG 4; 3300; ¶[0049]) and a transparent mold (FIG 2; 230; ¶[0053]) on the sensor (FIG 2; 200; ¶[0038]) to form a sensor assembly (FIG 2 and FIG 4; 200; 3300; 230; 200; ¶[0038] ¶[0049] ¶[0053]);
providing a substrate (FIG 2; 100; ¶[0025]), wherein one or more connectors (FIG 4; 204 and 202; ¶[0036]) are attached on a front surface of the substrate (FIG 2; 100; ¶[0025]);
forming a first encapsulant layer (FIG 2; 104; ¶[0028]) on the front surface of the substrate (FIG 2; 100; ¶[0025]), wherein the one or more connectors (FIG 4; 204 and 202; ¶[0036]) are exposed from the first encapsulant layer (FIG 2; 104; ¶[0028]);
disposing the sensor assembly (FIG 2 and FIG 4; 200; 3300; 230; 200; ¶[0038] ¶[0049] ¶[0053]) on the first encapsulant layer (FIG 2; 104; ¶[0028]);
connecting the sensor (FIG 2; 200; ¶[0038]) with the one or more connectors (FIG 4; 204 and 202; ¶[0036]); and
forming a second encapsulant layer (FIG 2; 220; ¶[0025]) on the first encapsulant layer (FIG 2; 104; ¶[0028]) to cover the sensor assembly (FIG 2 and FIG 4; 200; 3300; 230; 200; ¶[0038] ¶[0049] ¶[0053]).
Regarding Claim 5, the method of claim 1, FIG 2 discloses wherein before forming a first encapsulant layer (FIG 2; 104; ¶[0028]) on the front surface of the substrate (FIG 2; 100; ¶[0025]), the method further comprises:
attaching one or more electronic components (FIG 2; 110; ¶[0027]) on the front surface of the substrate (FIG 2; 100; ¶[0025]).
Regarding claim 6, the method of claim 5, Fig 2 and FIG 4 disclose wherein the one or more electronic components (FIG 2; 110; ¶[0027]) are electrically coupled to the one or more connectors (FIG 4; 204 and 202; ¶[0036]).
Regarding Claim 8, The method for claim 1, FIG 2 discloses wherein the one or more connectors (FIG 4; 204 and 202; ¶[0036]) comprise one or more metal bars (FIG 4; 202; ¶[0036]).
Regarding Claim 9, the method for claim 1, FIG 2 discloses wherein the one or more connectors (FIG 4; 204 and 202; ¶[0036]) comprise one or more vertical bonding wires (FIG 2; 204; ¶[0036]).
Regarding Claim 10, FIG 2 and FIG 4 disclose a sensor package, comprising:
a substrate (FIG 2; 100; ¶[0025]);
one or more electronic components (FIG 2; 110; ¶[0027) formed on the substrate (FIG 2; 100; ¶[0025]);
one or more connectors (FIG 4; 204 and 202; ¶[0036]) formed on the substrate (FIG 2; 100; ¶[0025]);
a first encapsulant layer (FIG 2; 104; ¶[0028]) for encapsulating the one or more electronic components (FIG 2; 110; ¶[0027) and the one or more connectors (FIG 2; 204; ¶[0036]), wherein the one or more connectors (FIG 2; 204; ¶[0036]) are exposed from a front surface of the first encapsulant layer (FIG 2; 104; ¶[0028]);
a sensor (FIG 2 and FIG 4; 200; ¶[0038]) formed on the first encapsulant layer and electrically coupled to the one or more connectors (FIG 4; 204 and 202; ¶[0036]), wherein the sensor is formed on the first encapsulant layer (FIG 2; 104; ¶[0028]);
an optical filter (FIG 4; 3300; ¶[0049]) formed on the sensor (FIG 2 and FIG 4; 200; ¶[0038]);
a transparent mold (FIG 2; 230; ¶[0025]) formed on the optical filter (FIG 4; 3300; ¶[0049]); and
a second encapsulant layer encapsulating the sensor (FIG 2 and FIG 4; 200; ¶[0038]), the optical filter (FIG 4; 3300; ¶[0049]) and the transparent mold (FIG 2; 230; ¶[0025]).
Regarding Claim 11, The sensor package of claim 10, FIG 4 disclose wherein the one or more connectors (FIG 4; 204 and 202; ¶[0036]) comprise one or more metal bars (FIG 4; 204; ¶[0036]).
Regarding Claim 12, the sensor package of claim 10, FIG 2 disclose wherein the one or more connectors (FIG 2; 202; ¶[0036]) comprise one or more vertical bonding wires (FIG 2; 204; ¶[0036]).
Regarding Claim 13, The sensor package of claim 10, FIG 4 discloses wherein the sensor (FIG 2 and FIG 4; 200; ¶[0038]) comprises an optical sensor (FIG 4; 200; image sensor chip; ¶[0126]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Kim-1(US20240038795A1) as applied to claim 1 above, and further in view of Kim-2(20240250100A1).
Regarding Claim 2, Kim -1 teaches in FIG 2 the method for claim 1, wherein providing a sensor (FIG 2; 200; ¶[0025]) comprises
Kim-1 does not teach forming a patterned photoresist layer on the sensor.
Kim-2 teaches in FIG 4 forming a patterned photoresist layer (FIG 4; 65; ¶[0085]) on the sensor (FIG 4; 10; ¶[0083])
It is obvious to one with ordinary skill in the art before the effective filing date of the invention of Kim-1, a semiconductor device providing a sensor, and the invention of Kim-2, a semiconductor device forming a patterned photoresist layer on a sensor. This combination produces a semiconductor device providing a sensor forming a patterned photoresist layer on the sensor. The photoresist layer acts as a spacer between the sensor and the transparent substrate (Kim-2 ¶[0084]).
Claim 3 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Kim-1(US20240038795A1) and Kim-2(US20240250100A1) as applied to claim 2 above, and further in view of Yun(US20240030254A1).
Regarding Claim 3, Kim-1 and Kim-2 teach the method for claim 2,
Kim-1 teaches in FIG 2 and FIG 4 wherein forming an optical filter and a transparent mold on the sensor comprises:
forming an optical filter (FIG 4; 3300; ¶[0049]) layer on the sensor (FIG 2; 200; ¶[0038]);
forming a transparent encapsulant layer (FIG 2; 230; ¶[0053]) on the optical filter (FIG 4; 3300; ¶[0049]) layer; and
Kim-1 does not teach removing a portion of the optical filter layer and a portion of the transparent encapsulant layer to form the optical filter and the transparent mold, so as to expose the patterned photoresist layer on the sensor.
Yun teaches in FIG 2 and FIG 4, removing a portion of the optical filter layer (FIG 4; LB1 and LB2; ¶[0063]; a reflow process may be performed on the photoresist patterns to form the first and second lens bar patterns LB1 and LB2 having round shapes) and a portion of the transparent encapsulant layer (FIG 2; 300; ¶[0036]; an empty space may be provided between the transparent substrate 300 and the image sensor chip C1 by the dam structure 200) to form the optical filter (FIG 4; MLA; ¶[0031]) and the transparent mold (FIG 2; 300; ¶[0018]), so as to expose the patterned photoresist layer (FIG 4; photoresist pattern; ¶[0063]) on the sensor (FIG 4; C1; ¶[0018]).
It is obvious to one with ordinary skill in the art before the effective filing date of the invention to combine the prior art of Kim-1 and Kim-2, a semiconductor device with a senor, optical filter layer and transparent layer, and the prior art of Yun, a semiconductor device fabricated by depositing photoresist on the surface and forming an optical filter layer and displacing/removing the transparent layer with a spacer. This combination produces a semiconductor device with a sensor, optical filter layer fabricated by depositing photoresist on the surface, and a transparent layer displayed/removed with a spacer. The patter from the photoresist translates to the lens patterns in the optical filter unit Yun[0063].
Regarding Claim 4, Kim-1 and Kim-2 teach the method for claim 3.
Kim-1 does not teach wherein forming an optical filter and a transparent mold on the sensor comprises further comprises:
after removing a portion of the optical filter layer and a portion of the transparent encapsulant layer, removing the patterned photoresist layer from the sensor.
Yun teaches in FIG 2 and FIG 4, wherein forming an optical filter (FIG 4; MLA; ¶[0031]) and a transparent mold (FIG 2; 300; ¶[0018]) on the sensor (FIG 4; C1; ¶[0018]) comprises further comprises:
after removing a portion of the optical filter layer (FIG 4; LB1 and LB2; ¶[0063]; a reflow process may be performed on the photoresist patterns to form the first and second lens bar patterns LB1 and LB2 having round shapes) and a portion of the transparent encapsulant layer (FIG 2; 300; ¶[0036]; an empty space may be provided between the transparent substrate 300 and the image sensor chip C1 by the dam structure 200), removing the patterned photoresist layer (FIG4; photoresist layer no longer on surface of device; passivation layer (PL) directly onto of microlenses (ML)) from the sensor (FIG 4; C1; ¶[0018]).
It is obvious to one with ordinary skill in the art before the effective filing date of the invention to combine the prior art of Kim-1 and Kim-2, a semiconductor device with a senor, optical filter layer and transparent layer, and the prior art of Yun, a semiconductor device fabricated by depositing photoresist on the surface and forming an optical filter layer and displacing/removing the transparent layer with a spacer and removing the patterned photoresist layer. This combination produces a semiconductor device with a sensor, optical filter layer fabricated by depositing photoresist on the surface, a transparent layer displayed/removed with a spacer and no photoresist present on the surface of the sensor. The photoresist being removed from the surface of the senor allows for the passivation layer (PL) to be deposited on the surface of the sensor and the microlenses Yun[0066].
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Kim-1(US20240038795A1) as applied to claim 1 above, and further in view of Newman(GB2100508A).
Kim-1 teaches Regarding Claim 7, the method for claim 1, wherein forming a first encapsulant layer (FIG 2; 104; ¶[0028]) on the front surface of the substrate (FIG 2; 100; ¶[0025]) further comprises:
the first encapsulant layer (FIG 2; 104; ¶[0028]) to expose the one or more connectors (FIG 4; 204 and 202; ¶[0036]).
Kim-1 does not teach grinding a portion of
Newman teaches grinding a portion (Page 1 Col 2 Line 114-122)
It is obvious to one with ordinary skill before the effective filing date of the invention to combine the prior art of Kim-1, a semiconductor device with a senor, a first encapsulant layer and connectors, and the prior art of Newman, s method to grind away at passivation material and expose the underlaying semiconductor material for connections. This combination would produce a method to form a semiconductor device by grinding away at the encapsulation material to expose the connectors. This method produces electrical electrically conductive contact regions on the surface in localized regions (Page 1 Col 2 Ln 110-113).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s
disclosure:
Chen(US20220293651A1); This reference discloses a semiconductor device that uses photolithography and plasma etching in the assembly process.
Cheng(US20230238408A1); This reference teaches a semiconductor package with a first encapsulating layer and a second encapsulating layer
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BASEEMAH QADEER RUCKER whose telephone number is (571)272-0380. The examiner can normally be reached Monday-Friday 7:30-5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at 5712727925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/B.Q.R./Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
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