DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election
Applicant’s election of claims #14-20 in the reply filed on June 22, 2026 is acknowledged. Because the Applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.03(a)).
IDS
The IDS document(s) filed on May 24, 2024 and October 29, 2024 and October 29, 2025 have been considered. Copies of the PTO-1449 documents are herewith enclosed with this office action.
Claim Objections
As to claim 21, the Examiner suggests “patterning a
Drawing Objections
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “gate structure over and along sidewalls of the first semiconductor fin” (emphasis added) as recited in claim 1 and “after removing the sacrificial material, forming a gate stack around the first nanostructures” and “forming a dummy gate over and along sidewalls of the first nanostructures” as recited in claims 21 and 26 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections – 35 U.S.C. § 112(b)
The following is a quotation of 35 U.S.C. § 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 14-29 are rejected under 35 U.S.C. § 112(b) or pre-AIA 35 U.S.C. § 112, second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant, regards as the invention.
As to claim 14, it is unclear how a gate structure 76 is formed along sidewalls of the first semiconductor fin 66. The Examiner instead assumes the gate structure is formed along sidewalls of the nanostructures 55.
As to claim 21, there is a lack of antecedent basis for “removing a sacrificial material from between the first nanostructures” as the first nanostructures were not recited as having a sacrificial material therebetween.
As to claims 21 and 26, it is unclear how “after removing the sacrificial material, forming a gate stack around the first nanostructures” and “further comprising: forming a dummy gate over and along sidewalls of the first nanostructures” (emphasis added) are consonant with each other. In claim 21, FIGS. 20A-22A, after removing the sacrificial material 72, forming a gate stack 102 around the first nanostructures. In claim 26, it is unclear how claim 21 further comprises forming a dummy gate 76 over and along sidewalls of the first nanostructures when this step precedes the recitation of claim 21 and is shown in FIGS. 19A-20A.
Indication of Allowable Subject Matter
Claims 14-29 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
As to claim 14, Chen et al. (U.S. Patent Publication No. 2022/0238716 A1), hereafter “Chen”, teaches etching a trench (FIG. 2B) in a substrate to define a first semiconductor fin 110a and a second semiconductor fin 110a; forming a shallow trench isolation (STI) region 112, 114a in the trench; forming a first hard mask 210 over the STI region; forming (FIG. 1H) a gate structure 118 over and along sidewalls of the first semiconductor fin However, Chen does not teach inter alia forming a second hard mask, the gate structure covers at least a portion of the second hard mask.
As to claim 21, Jhan et al. (U.S. Patent Publication No. 2022/0059678 A1), hereafter “Jhan”, teaches patterning a semiconductor fin (portion 12 of 28) extending from a substrate 10 and first nanostructures 14, 16 that are vertically stacked over the semiconductor fin; forming an isolation structure 32 adjacent to the semiconductor fin; forming a first hard mask material 34 over the isolation structure; forming a second hard mask material 36 over the first hard mask material; forming a gate stack 46 around the first nanostructures. However, Jhan does not teach inter alia removing a sacrificial material.
The following is a statement of reasons for the indication of allowable subject matter: claims 30-33 are indicated as being allowable because prior art fails to teach “wherein the gate structure overlaps the semiconductor hard mask” as recited in claim 30.
As to claim 30, Jhan teaches patterning a first fin and a second fin (portions 12 of 28), a first stack of nanostructures 14, 16 over the first fin, and a second stack of nanostructures (adjacent 14, 16) over the second fin; forming an isolation structure 32 between the first fin and the second fin; depositing a semiconductor material layer 34, 36 (dielectric materials that contain silicon semiconductor) over and along sidewalls of the first stack of nanostructures and the second stack of nanostructures, wherein the semiconductor material layer overlaps the isolation structure (FIG. 6); removing (FIG. 7) an upper portion and sidewall portions of the semiconductor material layer; forming a gate structure 46 over and along sidewalls of the first stack of nanostructures and the second stack of nanostructures. However, Jhan does not teach using a non-conformal deposition process, removing the portions of the semiconductor material layer to form a semiconductor hard mask, and wherein the gate structure overlaps the semiconductor hard mask.
Prior Art Not Relied Upon
The following prior art was not relied upon but is made of record:
Li et al. (U.S. Patent Publication No. 2021/0242334 A1)
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUBERR CHI whose telephone number is (571)270-3955. The examiner can normally be reached 10am to 6pm.
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/SUBERR L CHI/Primary Examiner, Art Unit 2893
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