Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 05/06/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the Examiner.
Election/Restrictions
Applicant’s election of claims 13-18, 21-34 without traverse in the reply filed on 07/15/2026 is acknowledged.
However, newly submitted claim 31 is directed to an invention that is independent or distinct from the invention originally claimed for the following reasons:
Inventions II and the Invention claimed in claim 31 are related as subcombinations disclosed as usable together in a single combination. This is because one larger device may contain both Invention II and the Invention claimed in claim 31. The subcombinations are distinct if they do not overlap in scope and are not obvious variants, and if it is shown that at least one subcombination is separately usable. In the instant case, the Invention claimed in claim 31 has separate utility. This is because the Invention claimed in claim 31 may be the only Invention in a larger device. This is because both Invention II and the Invention claimed in claim 31 each have a DTI which isolates a transistor from a high-power transistor. The geometries of the DTIs of Invention II and the Invention claimed in claim 31 are mutually exclusive. See MPEP § 806.05(d).
The examiner has required restriction between subcombinations usable together. Where applicant elects a subcombination and claims thereto are subsequently found allowable, any claim(s) depending from or otherwise requiring all the limitations of the allowable subcombination will be examined for patentability in accordance with 37 CFR 1.104. See MPEP § 821.04(a). Applicant is advised that if any claim presented in a divisional application is anticipated by, or includes all the limitations of, a claim that is allowable in the present application, such claim may be subject to provisional statutory and/or nonstatutory double patenting rejections over the claims of the instant application.
Since applicant has received an action on the merits for the originally presented invention, that is Invention II, this invention has been constructively elected by original presentation for prosecution on the merits. Accordingly, claim 31 is withdrawn from consideration as being directed to a non-elected invention. See 37 CFR 1.142(b) and MPEP § 821.03.
To preserve a right to petition, the reply to this action must distinctly and specifically point out supposed errors in the restriction requirement. Otherwise, the election shall be treated as a final election without traverse. Traversal must be timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are subsequently added, applicant must indicate which of the subsequently added claims are readable upon the elected invention.
Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 13-17, 21-25, 27-30 and 32-34 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hu et al US 20190096744 A1. Hu et al will be referenced to as Hu henceforth.
Regarding Claim 13,
Hu teaches:
“A method for manufacturing an IC structure (FIG. 3), the method comprising:
forming an epitaxial layer (upper semiconductor layer 108, [0024]) on a semiconductor substrate (substrate 102, [0024]);
forming a trench through the epitaxial layer to interpose (first deep trench 142, [0063], FIG. 2F) between a first device region (annotated FIG. 3 #1) for a first transistor device having a first-type doped well (NMOS 260, [0072]: an NMOS is n-doped) and a second device region (annotated FIG. 3 #1); and
filling the trench with a complementary-type doped semiconductor fill to generate a deep trench isolation (DTI) structure (first trench fill material 118, [0028], claims 5, 9, and 10, FIG. 3: 118 and 102 have a first conductivity type. 102 is p-type. Therefore 118 is p-type.).”
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Annotated FIG. 3 #1
Regarding Claim 14,
Hu teaches:
“The method of claim 13, further comprising forming dielectric sidewalls in the trench prior to filling the trench with the complementary-type doped semiconductor fill (first dielectric liner 116, [0027], FIGs. 2G-H).”
Regarding Claim 15,
Hu teaches:
“The method of claim 13, wherein:
forming the trench comprises extending the trench into the semiconductor substrate (FIGs. 2E-F: The trench is extended into 104 which is part of 102.); and filling the trench with the complementary-type doped semiconductor fill comprises having the complementary-type doped semiconductor fill conductively connected to the semiconductor substrate (doped region 117, [0028], FIG. 3: 117 is conductively coupled to 118 and 102. Therefore 118 is conductively coupled to 102.).”
Regarding Claim 16,
Hu teaches:
“The method of claim 15, further comprising, after forming the trench and before filling the trench, enhanced doping a neighboring region of the semiconductor substrate underneath the trench with a complementary-type dopant ([0024], [0027], FIGs. 2G-H: 117 is doped with a dopant of a same conductivity as 104. 104 is part of 102 and is therefore p-type doped. Therefore 117 is p-type doped.), wherein, after filling the trench, the neighboring region is contiguous with the complementary-type doped semiconductor fill (FIG. 3).”
Regarding Claim 17,
Hu teaches:
“The method of claim 13, wherein forming the trench comprises forming a moat laterally surrounding the first device region (transistor well 101, pwell 225, [0022], [0072], FIG. 1A, FIG. 3: One of ordinary skill in the art would understand that the pwell is a transistor well. Because the pwell is a transistor well which is not part of a DMOS, one of ordinary skill in the art would understand that it is clear that the pwell corresponds to the transistor well.).”
Regarding Claim 21,
Hu teaches:
“A method for manufacturing an IC structure (FIG. 3), the method comprising: selectively depositing a first-type doped semiconductor fill (first trench fill material 118, [0028], [0067], claims 5, 9, and 10, FIGs. 2F-H FIG. 3: 118 and 102 have a first conductivity type. 102 is p-type. Therefore 118 is p-type.) on a semiconductor substrate (substrate 102, [0024]); forming an epitaxial layer on the semiconductor substrate around the first-type doped semiconductor fill (upper semiconductor layer 108, [0024]); and forming a first device region (annotated FIG. 3 #1) for a first transistor device having a complementary- type doped well ([0072], FIG. 3: The NMOS 260 may be replaced with a PMOS by changing the doping types relative to other NMOS devices in IC 300. One of ordinary skill in the art would understand that this entails changing the NMOS’s pwell into a nwell as a PMOS requires a nwell to function.) and a second device region (annotated FIG. 3 #1), wherein the first-type doped semiconductor fill forms a deep trench isolation (DTI) structure interposing between the first device region and the second device region (FIG. 3).”
Regarding Claim 22,
Hu teaches:
“The method of claim 21, further comprising forming dielectric sidewalls around the DTI structure, separating the DTI structure from the epitaxial layer (first dielectric liner 116, [0027], FIGs. 2G-H).”
Regarding Claim 23,
Hu teaches:
“The method of claim 21, wherein the first-type doped semiconductor fill is conductively connected to the semiconductor substrate (doped region 117, [0028], FIG. 3: 117 is conductively coupled to 118 and 102. Therefore 118 is conductively coupled to 102.).”
Regarding Claim 24,
Hu teaches:
“The method of claim 21, further comprising, before depositing the first-type doped semiconductor fill, enhanced doping a neighboring region of the semiconductor substrate underlying a location for the first-type doped semiconductor fill with a first-type dopant ([0024], [0027], FIGs. 2G-H: 117 is doped with a dopant of a same conductivity as 104. 104 is part of 102 and is therefore p-type doped. Therefore 117 is p-type doped.), wherein, after forming the DTI structure, the neighboring region is contiguous with the first-type doped semiconductor fill (FIG. 3).”
Regarding Claim 25,
Hu teaches:
“The method of claim 21, wherein the DTI structure forms a moat laterally surrounding the first device region (transistor well 101, [0022], [0072], FIG. 1A, FIG. 3: One of ordinary skill in the art would understand that a pwell is a transistor well. Because the pwell is a transistor well which is not part of a DMOS, one of ordinary skill in the art would understand that the pwell corresponds to the transistor well. Since the pwell 225 is replaced with a nwell, the nwell corresponds to a transistor well.).”
Regarding Claim 27,
Hu teaches:
“A method for forming an IC structure (FIG. 3), the method comprising: depositing an epitaxial layer (upper semiconductor layer 108, [0024]) over a semiconductor substrate (substrate 102, [0024]); using a first-type dopant (n-type) to form a first-type doped well in the epitaxial layer (n-body region 259, [0072], FIG. 3), the first-type doped well defining a first device region (annotated FIG. 3 #2); etching a trench in the epitaxial layer (first deep trench 142, [0063], FIG. 2F), the trench separating the first device region from a second device region (FIG. 3); and depositing a complementary-type doped semiconductor fill to fill the trench and form a trench isolation structure (first trench fill material 118 , [0028], claims 5, 9, and 10, FIG. 3: 118 and 102 have a first conductivity type. 102 is p-type. Therefore 118 is p-type.).”
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Annotated FIG. 3 #2
Regarding Claim 28,
Hu teaches:
“The method of claim 27, further comprising, prior to depositing the complementary-type doped semiconductor fill, depositing dielectric material in the trench to coat the trench with the dielectric material and form a sidewall structure (first dielectric liner 116, [0027], FIGs. 2G-H).”
Regarding Claim 29,
Hu teaches:
“The method of claim 28, further comprising etching dielectric material in the trench to remove a bottom section of the sidewall structure and define a dielectric sidewall for the trench isolation structure ([0064], [0066], FIG. 2G: Though not shown in FIG. 2G, dielectric 116 is deposited at the bottom of trench 142. This bottom portion is then etched in order for the formation of 117 to occur.).”
Regarding Claim 30,
Hu teaches:
“The method of claim 29, further comprising enhanced doping a semiconductor region neighboring a bottom of the trench to form a neighboring region (doped region 117, [0028], [0027], FIGs. 2G-H: 117 is doped with a dopant of the same conductivity as 104. 104 is part of 102 and is therefore p-type doped. Therefore 117 is p-type doped.).”
Regarding Claim 32,
Hu teaches:
“The method of claim 30, wherein:the etching of the trench in the epitaxial layer further comprises etching the trench into the semiconductor substrate (FIGs. 2E-F: The trench is extended into 104 which is part of 102.); and
the semiconductor region neighboring the bottom of the trench is in the semiconductor substrate (FIG. 3).”
Regarding Claim 33,
Hu teaches:
“The method of claim 27, wherein the etching of the trench in the epitaxial layer further comprises etching the trench into the semiconductor substrate (FIGs. 2E-F: The trench is extended into 104 which is part of 102.).”
Regarding Claim 34,
Hu teaches:
“The method of claim 27, wherein the method reduces an ability of charge carriers to flow in unintended paths in the IC structure ([0003]: The purpose of the device’s isolation structures and buried layer is to protect a low voltage transistor from a high voltage transistor. One of ordinary skill in the art would understand that a high voltage transistor will damage a low voltage transistor by creating unintended currents which heat up the low voltage transistor which in turn renders the low voltage transistor inoperable. Therefore, the device’s isolation structures and buried layer prevent an ability for charge carriers to flow in unintended paths.).”
Claims 13 and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cai US 20160043217 A1.
Regarding Claim 13,
Cai teaches:
“A method for manufacturing an IC structure (FIG. 13), the method comprising:
forming an epitaxial layer (p-epi region 1316, [0049]) on a semiconductor substrate (substrate 1310, [0049]);
forming a trench through the epitaxial layer to interpose (deep trench isolation structure 1301, [0049]) between a first device region (annotated FIG. 13 #1) for a first transistor device (CMOS region 1302, [0049]) having a first-type doped well (shallow N-well 1372, [0049]: A first type is n-type.) and a second device region (annotated FIG. 13 #1); and
filling the trench with a complementary-type doped semiconductor fill to generate a deep trench isolation (DTI) structure (p-type material 1364, [0049]: a complementary type is positive.).”
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Cai: annotated FIG. 13 #1
Regarding Claim 18,
Cai teaches:
“The method of claim 13, further comprising, (p-epitaxial layer 1212/1312, [0028] [0044], [0047], [0049], FIG. 3, FIGs. 12-13: Element 1312 is not listed in the description. However, FIG. 13 is the completed version of FIG. 12. Therefore layers 1312 and 1212 are the same layer under different labels as they occupy the same position. Similarly, 1312 is the completed version of element 312 in FIG. 3.), the buried doped barrier layer doped with a complementary-type dopant (P-type is complementary to n-type.).”
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 21 and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Cai as applied to claims 13 and 18 above, and further in view of Yu.
Regarding Claim 21,
Cai teaches:
“A method for manufacturing an IC structure (FIG. 13), on a semiconductor substrate (substrate 1310, [0049]); forming an epitaxial layer on the semiconductor substrate around the first-type doped semiconductor fill (p-epitaxial layer 1212/1312, [0044], [0047], [0049], FIGs. 12-13: Element 1312 is not listed in the description. However, FIG. 13 is the completed version of FIG. 12. Therefore layers 1312 and 1212 are the same layer under different labels as they occupy the same position.); and forming a first device region (CMOS region 1302, [0049]) for a first transistor device having a complementary- type doped well (shallow N-well 1372, [0049]) and a second device region (LDMOS device 1300, [0049]), wherein the first-type doped semiconductor fill forms a deep trench isolation (DTI) structure interposing between the first device region and the second device region (FIG. 13).”
Cai doesn’t substantially teach:
“selectively depositing a first-type doped semiconductor fill”
However, Yu teaches:
“selectively depositing a first-type doped semiconductor fill (first trench fill material 118, [0028], [0067], claims 5, 9, and 10, FIGs. 2F-H FIG. 3: 118 and 102 have a first conductivity type. 102 is p-type. Therefore 118 is p-type. 144, which makes up 118 is deposited into 142 in FIGs. 2F-G.)”
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the invention to recognize that the device of Cai is modifiable in view of Yu by using the deposition process of Yu to form the first-type doped semiconductor fill.
This is because one of ordinary skill in the art would be motivated to find a method of forming a first-type doped semiconductor fill in order to form the device of Cai. The method of Yu successfully deposits a first-type doped semiconductor fill.
Regarding Claim 26,
Cai/Yu teaches:
“The method of claim 21, further comprising forming a buried doped barrier layer in the first device region (p-type buried layer PBL 1328, [0049]), the buried doped barrier layer doped with first-type dopant (The PBL is p-type.).”
Conclusion
The prior arts made of record and not relied upon are US 20160163583 A1 and US 20200403072 A1 are considered pertinent to applicant's disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDRE XAVIER RAMIREZ whose telephone number is (571)272-2715. The examiner can normally be reached Monday - Friday 8:30 AM to 6:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ALEXANDRE X RAMIREZ/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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