Prosecution Insights
Last updated: August 16, 2026
Application No. 18/673,978

ELECTRONIC PACKAGE AND MANUFACTURING METHOD THEREOF

Non-Final OA §102§103
Filed
May 24, 2024
Priority
Nov 27, 2023 — TW 112145870
Examiner
KIM, TONG-HO
Art Unit
Tech Center
Assignee
Siliconware Precision Industries Co., Ltd.
OA Round
1 (Non-Final)
95%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
96%
With Interview

Examiner Intelligence

Grants 95% — above average
95%
Career Allowance Rate
1034 granted / 1086 resolved
+35.2% vs TC avg
Minimal +1% lift
Without
With
+0.7%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 8m
Avg Prosecution
37 currently pending
Career history
1100
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
46.3%
+6.3% vs TC avg
§102
31.2%
-8.8% vs TC avg
§112
9.0%
-31.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1086 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 5-11 and 15-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Han (US 2021/0366838). Regarding claim 1, Han discloses, in at least figures 7A-7C and related text, an electronic package, comprising: a carrier structure (713, [43]) having a first surface (upper surface of 713, figures), a second surface (lower surface of 713, figures) opposing the first surface (upper surface of 713, figures), and a side surface (side surface of 713, figures) adjacent to the first surface (upper surface of 713, figures) and the second surface (lower surface of 713, figures), wherein the side surface (side surface of 713, figures) is formed with a recess (732, [44], figures); a package module (IC dies of 106, [27]) disposed on the first surface (upper surface of 713, figures) of the carrier structure (713, [43]); and a shielding layer (704, [43]) formed on the first surface (upper surface of 713, figures) of the carrier structure (713, [43]) and covering the package module (IC dies of 106, [27]), wherein the shielding layer (704, [43]) is further formed on a part of the side surface (side surface of 713, figures) of the carrier structure (713, [43]) rather than on the recess (732, [44], figures). Regarding claim 5, Han discloses the electronic package of claim 1 as described above. Han further discloses, in at least figures 7A-7C and related text, the recess (732, [44], figures) is adjacent to the second surface (lower surface of 713, figures) and the side surface (side surface of 713, figures), and an edge of the carrier structure (713, [43]) has a notched appearance (figures). Regarding claim 6, Han discloses the electronic package of claim 1 as described above. Han further discloses, in at least figures 7A-7C and related text, the carrier structure (713, [43]) is an antenna substrate ([43]). Regarding claim 7, Han discloses the electronic package of claim 6 as described above. Han further discloses, in at least figures 7A-7C and related text, the carrier structure (713, [43]) has an antenna portion (portion of 734, [43]), and the shielding layer (704, [43]) is not formed on the side surface corresponding to the antenna portion (portion of 734, [43]). Regarding claim 8, Han discloses the electronic package of claim 1 as described above. Han further discloses, in at least figures 7A-7C and related text, the shielding layer (704, [43]) is not formed on the second surface (lower surface of 713, figures) of the carrier structure (713, [43]). Regarding claim 9, Han discloses the electronic package of claim 1 as described above. Han further discloses, in at least figures 7A-7C and related text, the package module (IC dies of 106, [27]) comprises at least one electronic component (108, [27]) electrically connected to the carrier structure (713, [43]), and an encapsulation layer (117, [28]) covering the electronic component (108, [27]), wherein the shielding layer (704, [43]) is formed on the encapsulation layer (117, [28]). Regarding claim 10, Han discloses the electronic package of claim 9 as described above. Han further discloses, in at least figures 7A-7C and related text, the package module (IC dies of 106, [27]) further comprises a circuit structure (RF ICs of 108, [28]) carrying the electronic component (108, [27]), wherein the circuit structure (RF ICs of 108, [28]) is disposed on the first surface (upper surface of 713, figures) of the carrier structure (713, [43]) via a plurality of conductive components (119, [28]). Regarding claim 11, Han discloses, in at least figures 13A-13D and related text, a method of manufacturing an electronic package, comprising: providing at least one package module (IC dies of 106, [27]) on a carrier structure (713, [43]), wherein the carrier structure (713, [43]) has a first surface (upper surface of 713, figures), a second surface (lower surface of 713, figures) opposing the first surface (upper surface of 713, figures), and a side surface (side surface of 713, figures) adjacent to the first surface (upper surface of 713, figures) and the second surface (lower surface of 713, figures), wherein the package module (IC dies of 106, [27]) is disposed on the first surface (upper surface of 713, figures) of the carrier structure (713, [43]); forming a shielding layer (704 (702), [43]) on the first surface (upper surface of 713, figures) and the side surface (side surface of 713, figures) of the carrier structure (713, [43]) to cover the package module (IC dies of 106, [27]); and forming a recess (732, [44]) on the side surface (side surface of 713, figures) of the carrier structure (713, [43]) to remove a portion of the shielding layer (704 (702), [43]) on the side surface (side surface of 713, figures) of the carrier structure (713, [43]) corresponding to the recess (732, [44]), so that the shielding layer (704 (702), [43]) is formed on a part of the side surface (side surface of 713, figures) rather than on the recess (732, [44]). Regarding claim 15, Han discloses the method of claim 11 as described above. Han further discloses, in at least figures 13A-13D and related text, the recess (732, [44], figures) is adjacent to the second surface (lower surface of 713, figures) and the side surface (side surface of 713, figures), and an edge of the carrier structure (713, [43]) has a notched appearance (figures). Regarding claim 16, Han discloses the method of claim 11 as described above. Han further discloses, in at least figures 13A-13D and related text, the carrier structure (713, [43]) is an antenna substrate ([43]). Regarding claim 17, Han discloses the method of claim 16 as described above. Han further discloses, in at least figures 13A-13D and related text, the carrier structure (713, [43]) has an antenna portion (portion of 734, [43]), and the shielding layer (704, [43]) is not formed on the side surface corresponding to the antenna portion (portion of 734, [43]). Regarding claim 18, Han discloses the method of claim 11 as described above. Han further discloses, in at least figures 13A-13D and related text, the shielding layer (704, [43]) is not formed on the second surface (lower surface of 713, figures) of the carrier structure (713, [43]). Regarding claim 19, Han discloses the method of claim 11 as described above. Han further discloses, in at least figures 13A-13D and related text, the package module (IC dies of 106, [27]) comprises at least one electronic component (108, [27]) electrically connected to the carrier structure (713, [43]), and an encapsulation layer (117, [28]) covering the electronic component (108, [27]), wherein the shielding layer (704, [43]) is formed on the encapsulation layer (117, [28]). Regarding claim 20, Han discloses the method of claim 19 as described above. Han further discloses, in at least figures 13A-13D and related text, the package module (IC dies of 106, [27]) further comprises a circuit structure (RF ICs of 108, [28]) carrying the electronic component (108, [27]), wherein the circuit structure (RF ICs of 108, [28]) is disposed on the first surface (upper surface of 713, figures) of the carrier structure (713, [43]) via a plurality of conductive components (119, [28]). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 2-4 and 12-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Han (US 2021/0366838) in view of Lee (US 2023/0140748). Regarding claim 2, Han discloses the electronic package of claim 1 as described above. Han does not explicitly disclose the carrier structure has an insulating material and a wiring layer formed on the insulating material, and the wiring layer is electrically connected to the package module. Lee teaches, in at least figure 4 and related text, the device comprising the carrier structure (152/230, [22], [32]) has an insulating material (154, [22]) and a wiring layer (156, [22]) formed on the insulating material (154, [22]), and the wiring layer (156, [22]) is electrically connected to the package module (104, [21]), for the purpose of providing improved AiP decices ([5]). Han and Lee are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Han with the specified features of Lee because they are from the same field of endeavor. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Han to have the carrier structure having an insulating material and a wiring layer formed on the insulating material, and the wiring layer being electrically connected to the package module, as taught by Lee, for the purpose of providing improved AiP decices ([5], Lee). Regarding claim 3, Han discloses the electronic package of claim 1 as described above. Han does not explicitly disclose at least one electronic connector disposed on the carrier structure. Lee teaches, in at least figure 4 and related text, the device comprising at least one electronic connector (254, [34]) disposed on the carrier structure (152/230, [22], [32]), for the purpose of providing improved AiP decices ([5]). Han and Lee are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Han with the specified features of Lee because they are from the same field of endeavor. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Han to have the at least one electronic connector disposed on the carrier structure, as taught by Lee, for the purpose of providing improved AiP decices ([5], Lee). Regarding claim 4, Han in view of Lee discloses the electronic package of claim 3 as described above. Lee further teaches, in at least figure 4 and related text, the shielding layer (210, [29]) is not formed on the electronic connector (254, [34]), for the purpose of providing improved AiP decices ([5]). Regarding claim 12, Han discloses the method of claim 11 as described above. Han does not explicitly disclose the carrier structure has an insulating material and a wiring layer formed on the insulating material, and the wiring layer is electrically connected to the package module. Lee teaches, in at least figure 4 and related text, the method comprising the carrier structure (152/230, [22], [32]) has an insulating material (154, [22]) and a wiring layer (156, [22]) formed on the insulating material (154, [22]), and the wiring layer (156, [22]) is electrically connected to the package module (104, [21]), for the purpose of providing improved AiP decices ([5]). Han and Lee are analogous art because they both are directed to method for forming a semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Han with the specified features of Lee because they are from the same field of endeavor. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method disclosed in Han to have the carrier structure having an insulating material and a wiring layer formed on the insulating material, and the wiring layer being electrically connected to the package module, as taught by Lee, for the purpose of providing improved AiP decices ([5], Lee). Regarding claim 13, Han discloses the method of claim 11 as described above. Han does not explicitly disclose at least one electronic connector disposed on the carrier structure. Lee teaches, in at least figure 4 and related text, the method comprising at least one electronic connector (254, [34]) disposed on the carrier structure (152/230, [22], [32]), for the purpose of providing improved AiP decices ([5]). Han and Lee are analogous art because they both are directed to method for forming a semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Han with the specified features of Lee because they are from the same field of endeavor. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method disclosed in Han to have the at least one electronic connector disposed on the carrier structure, as taught by Lee, for the purpose of providing improved AiP decices ([5], Lee). Allowable Subject Matter Claim 14 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 1, 13, and 14 that recite "covering the electronic connector by a protective cover, and forming the shielding layer on the protective cover, then removing the protective cover to remove the shielding layer on the protective cover, so that the shielding layer is not formed on the electronic connector" in combination with other elements of the base claims 1, 13, and 14. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TONG-HO KIM whose telephone number is (571)270-0276. The examiner can normally be reached Monday thru Friday; 8:30 AM to 5PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at 571-272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TONG-HO KIM/ Primary Examiner, Art Unit 2811
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Prosecution Timeline

May 24, 2024
Application Filed
Jul 14, 2026
Non-Final Rejection mailed — §102, §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
95%
Grant Probability
96%
With Interview (+0.7%)
1y 8m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1086 resolved cases by this examiner. Grant probability derived from career allowance rate.

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