DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of species I in the reply filed on 8/5/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claims 11-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 8/5/2026.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-10 are rejected under 35 U.S.C. 103 as being unpatentable over PARK et al. (US PG Pub 2022/0005837, hereinafter Park) in view of WANG et al. (US PG Pub 2022/0336555, hereinafter Wang).
Regarding claim 1, figure 3 of Park discloses a display device comprising:
a barrier layer (110) on a substrate (100) and comprising a trench (TCH1);
a first buffer layer (130) on the barrier layer and arranged along a profile of the trench;
a semiconductor layer (141) on the buffer layer and comprising a channel region (141C) overlapping the trench;
a gate insulating layer (151) on the semiconductor layer and overlapping the channel region; and
a gate electrode (161) on the gate insulating layer and overlapping the channel region.
Park does not explicitly disclose a second buffer layer on the first buffer layer and arranged along a profile of the first buffer layer;
wherein the first buffer layer has a thickness that is thinner than a thickness of the second buffer layer.
In the same field of endeavor, Wang discloses a buffer layer can comprise a single or multiple buffer layers (¶ 57).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form a second buffer layer as taught by Wang for the purpose of substituting art recognized equivalents known to be used for the same purpose. see MPEP 2144.06.
Furthermore, the thickness of the second buffer layer can be measured at a diagonal such that it is thicker than a thickness of the first buffer layer (measured vertically).
Regarding claim 2, figure 3 of Park discloses the trench (TCH1) comprises a vertical portion connecting a portion having a thinnest thickness of the barrier layer (110) and a portion having a thickest thickness of the barrier layer,
the channel region has a depth corresponding to the vertical portion of the trench.
Park does not explicitly disclose the depth of the channel region is 330 Ǻ to 3500 Ǻ.
However, it would have been obvious to form the depth to be within the claimed range, since it has been held by the Federal circuit that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. (In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984)).
Regarding claim 3, Park does not explicitly disclose the channel region has a width of 5 µm or less.
However, it would have been obvious to form the channel region width to be within the claimed range, since it has been held by the Federal circuit that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. (In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984)).
Regarding claims 4-6, Wang discloses the first buffer layer comprises silicon nitride, and the second buffer layer comprises silicon oxide (¶ 57).
Furthermore regarding the limitations “the first buffer layer comprises a material of which an amount of hydrogen emission increases as a stack thickness increases” and “the second buffer layer comprises a material of which an amount of hydrogen emission is constant as a stack thickness increases”, it will be taken that the prior art discloses the same materials as claimed and thus will have the same characteristics as claimed.
Regarding claims 7 and 8, Park does not explicitly the first buffer layer has a thickness of 330 Ǻ to 1100 Ǻ, and the second buffer layer has a thickness of 1600 Ǻ to 2400 Ǻ, or
the gate insulating layer has a thickness of 650 Ǻ or more and 2000 Ǻ or less.
However, it would have been obvious to form the buffer layers and gate insulating layer to have thicknesses to be within the claimed ranges, since it has been held by the Federal circuit that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. (In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984)).
Regarding claim 9, the term “portions” is not well defined in the claim and arbitrary portions (having a founded shape) of the corner of the trench (TCH1) can be interpreted to read on the claimed limitations.
Regarding claim 10, Park does not explicitly disclose the gate insulating layer comprises at least one of Al2O3, TiO2, and HfO2.
However, it would have been obvious to use one of the claimed materials since they are well known in the art to be suitable for gate insulating layers.
Conclusion
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/YU-HSI D SUN/ Primary Examiner, Art Unit 2817
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