DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Objections
Claim 13 is objected to because of the following informalities: Correct the spelling of “deposing”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hou et al., US Publication No. 2017/0170027 A1.
Hou anticipates:
17. A method, comprising (see figs. 1 and 5-6):
depositing a high-k dielectric layer (HK, 506) within a trench (e.g. In fig. 1, trench where gate dielectric 112 is disposed. In fig. 5, trench to left/right of 504) and over a substrate (102, 502);
conformally depositing a titanium-containing nitride layer (TSN, 508) over the high-k dielectric layer;
performing a first annealing process (e.g. first anneal at para. [0021], [0032]) to the titanium-containing nitride layer;
conformally depositing a semiconductor layer (e.g. capping layer, 512) over the titanium-containing nitride layer;
performing a second annealing process (e.g. second anneal at para. [0021], [0036]) to the semiconductor layer;
after the performing of the second annealing process, selectively removing the titanium-containing nitride layer (e.g. See para. [0043] disclosing “However, in some embodiments and as shown in FIG. 5D, at least a portion of the conformal fluorinated barrier metal layer 508A may remain (e.g., after the PCA process 514),…” Because the disclosure indicates “at least a portion…remains”, this means a portion of the TSN layer 508A is etched during the removal of the capping layer. This etching of TSN layer 508A discloses the limitation “selectively removing” recited in the claim.) and the semiconductor layer (e.g. capping layer is removed at para. [0037], [0043]);
forming a work function layer (e.g. dual work function metal gate at para. [0020]) over the high-k dielectric layer and in the trench; and
forming a metal layer (e.g. dual work function metal gate at para. [0020]) over the work function layer and in the trench. See Hou at para. [0001] – [0052], figs. 1-8.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 4-8, 11, 12, 14 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsai et al., US Publication No. 2017/0032972 A1 in view of Kamineni et al., US Publication No. 2018/0174965 A1.
Tsai teaches:
1. A method, comprising (see figs. 5-17):
forming a gate spacer (82) over a substrate (70), wherein an inner sidewall of the gate spacer defines a trench (e.g. trench in fig. 8) over the substrate;
forming a conductive layer (96/98, e.g. barrier layer at para. [0044]) having a first portion in the trench and a second portion outside the trench, wherein the first portion in the trench comprises a vertical part and a horizontal part; …
forming a metal layer (122, e.g. cobalt) to fill the trench. See Tsai at para. [0001] – [0073], figs. 1-19.
Regarding claim 1:
Tsai does not expressly teach:
performing a first deposition process to form a first metal layer over the conductive layer, wherein the first metal layer has a first thickness on a sidewall surface of the vertical part and a second thickness on the horizontal part, the first thickness being different from the second thickness;
performing a second deposition process to form a conformal second metal layer over the first metal layer; and
forming a third metal layer over the second metal layer to fill the trench.
In an analogous art, Kamineni teaches:
(see figs. 1-11) forming a conductive layer (232/230, e.g. barrier layer at para. [0030]) having a first portion in the trench (220) and a second portion outside the trench (220), wherein the first portion in the trench comprises a vertical part and a horizontal part;
(see fig. 4) performing a first deposition process to form a first metal layer (250, e.g. cobalt) over the conductive layer, wherein the first metal layer has a first thickness on a sidewall surface of the vertical part and a second thickness on the horizontal part, the first thickness being different from the second thickness;
performing a second deposition process (e.g. See para. [0038] disclosing multiple cycles can be performed to form additional cobalt layers.) to form a conformal second metal layer (260, e.g. cobalt in fig. 10) over the first metal layer; and
forming a third metal layer (240, e.g. final filling cobalt layer) over the second metal layer to fill the trench. See Kamineni at para. [0022] – [0038].
Regarding claim 2:
Tsai further teaches:
2. The method of claim 1, further comprising:
before the forming of the conductive layer, forming a high-k dielectric layer (94) over the substrate and in the trench; and
forming a work function layer (100, 104) on the high-k dielectric layer and in the trench, para. [0043] – [0048].
Regarding claim 4:
Kamineni teaches wherein the first deposition process (e.g. forming 250, e.g. cobalt) comprises a chemical vapor deposition (CVD) process, para. [0032].
Kamineni does not expressly teach a directional physical vapor deposition (PVD) process.
However, Tsai teaches cobalt can be formed by CVD, PVD or combinations thereof at para. [0057].
Tsai teaches CVD, PVD or combinations thereof can be considered equivalent processes known in the art to deposit cobalt Therefore, because these processes were art-recognized equivalents, one of ordinary skill in the art would have found it obvious to substitute Kamineni’s first deposition process comprising CVD for PVD. Also see MPEP § 2144.06, Art Recognized Equivalence for the Same Purpose.
Regarding claim 5:
Kamineni further teaches:
5. The method of claim 4, wherein the second deposition process (e.g. forming 260) comprises a chemical vapor deposition (CVD) process, para. [0038], also see para. [0032].
Regarding claim 6:
Kamineni further teaches:
6. The method of claim 1, wherein the second metal layer (260) and the third metal layer (240) comprise cobalt, para. [0038].
Regarding claim 7:
Kamineni further teaches:
7. The method of claim 6, wherein the first metal layer (250) comprises cobalt, para. [0032].
Regarding claim 8:
Kamineni teaches in figs. 6-8 that the first metal layer (250) is oxidized to form layer (252) that is removed, which exposes the underlying conductive layer (232/230), para. [0034] – [0035].
One of ordinary skill in the art performing multiple cycles to form additional cobalt layers, as taught at para. [0038], would obviously form:
wherein a first portion of the second metal layer (260) is in direct contact with the conductive layer (232/230 in fig. 8), and a second portion of the second metal layer (260) is spaced apart from the conductive layer (232/230) by the first metal layer (e.g. remaining 250).
Tsai teaches:
11. A method, comprising (see figs. 5-17)
forming a gate dielectric layer (94) within a trench (e.g. trench in fig. 8);
forming a work function layer (100) over the gate dielectric layer;
forming a titanium-containing nitride layer (104) over the work function layer;…
forming a metal layer (122), thereby filling the trench. See Tsai at para. [0001] – [0073], figs. 1-19.
Tsai does not expressly teach:
forming a first metal layer over the titanium-containing nitride layer and in the trench, wherein the first metal layer has a non-uniform thickness;
forming a second metal layer over the first metal layer and in the trench, wherein the second metal layer has a uniform thickness; and
forming a third metal layer (240, e.g. final filling cobalt layer) over the second metal layer, thereby filling the trench.
In an analogous art, Kamineni teaches (see figs. 1-11):
(see fig. 4) forming a first metal layer (250, e.g. cobalt) a titanium-containing nitride layer (230, e.g. may comprise TiN, Co, etc. at para. [0029]) and in the trench (220), wherein the first metal layer has a non-uniform thickness;
forming a second metal layer (260, e.g. cobalt in fig. 10) over the first metal layer and in the trench (e.g. See para. [0038] disclosing multiple cycles can be performed to form additional cobalt layers.), wherein the second metal layer has a uniform thickness; and
forming a third metal layer over the second metal layer, thereby filling the trench. See Kamineni at para. [0022] – [0038].
Regarding claim 12:
Tsai further teaches:
12. The method of claim 11, wherein the work function layer comprises a titanium nitride (TiN) layer over a titanium aluminum carbide (TiAlC) layer (e.g. 100 is TiN, para. [0045])
Regarding claim 14:
Kamineni further teaches:
14. The method of claim 11, wherein the first metal layer (250), the second metal layer (260), and the third metal layer (240) have same composition (e.g. cobalt), para. [0032], [0038].
Regarding claim 15:
Kamineni further teaches:
15. The method of claim 11, wherein the first metal layer (250) comprises a first horizontal portion in the trench (220), a second horizontal portion outside the trench (220), and a vertical portion extending downwardly from the second horizontal portion, wherein the vertical portion has a non-uniform thickness, fig. 4.
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Tsai with the teachings of Kamenini because “Advantageously, the integrated circuit device fabrication processes disclosed herein provide for semiconductor devices having substantially void-free gap fill…” See Kamenini at para. [0021], also see para. [0003].
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsai in view of Kamineni, as applied to claim 1 above, in further view of Liu et al., US Publication No. 2015/0035062 A1.
Regarding claim 3:
Tsai further teaches:
3. The method of claim 2, wherein the high-k dielectric layer comprises hafnium oxide and contains Ti, Si, and N (e.g. See para. [0043] disclosing metal oxide or silicate of Hf, Ti and combinations thereof.)
Tsai does not expressly teach nitrogen (N).
In an analogous art, Liu teaches a gate dielectric can comprises hafnium silicon oxynitride, titanium nitride or “any suitable combination of those high-k materials” (e.g. HfSiON, TiN). See Liu at para. [0018].
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Tsai with the teachings of Liu
since it is within the general skill of a worker in the art to select known material on the basis of its suitability for the intended purpose as a matter of obvious design choice. In re Leshin, 125 USPQ 416. See MPEP § 2144.07, Art Recognized Suitability for an Intended Purpose. “Reading a list and selecting a known compound to meet known requirements is no more ingenious than selecting the last piece to put in the last opening in a jig-saw puzzle. 325 U.S. at 335, 65 USPQ at 301.”
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsai in view of Kamineni, as applied to claim 1 above, in further view of Murthy et al., US Patent No. 8,198,196.
Regarding claim 9:
Tsai and Kamineni teach all the limitations of claim 1 above, but do not expressly teach:
wherein the first thickness gradually increases from bottom to top.
In an analogous art, Murthy teaches:
(see fig. 2A) wherein the first thickness (e.g. of 220) gradually increases from bottom to top. See Murthy at col 4, ln 57–67, col 5, ln 1–10.
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Tsai and Kamineni with the teachings of Murthy because in “a conventional trench filling method” the deposited material by a chemical vapor deposition (CVD) or physical vapor deposition (PVD) process often is not conformal when the trench has a high aspect ratio. See Murthy at col 4, ln 57–67, col 5, ln 1–10.
Claim(s) 10 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsai in view of Kamineni, as applied to claims 1 and 11 above, in further view of Patil et al., US Patent No. 10,056,303.
Regarding claim 10:
Tsai and Kamineni teach all the limitations of claim 1 above, but do not expressly teach:
wherein a portion of the first metal layer on the horizontal part of the conductive layer has a convex top surface.
In an analogous art, Patil teaches:
(see fig. 1f) wherein a portion of the first metal layer (117) on the horizontal part of a conductive layer (115) has a convex top surface. See Patil at col 5, ln 40–65.
Regarding claim 16:
Kamineni further teaches:
wherein the first horizontal portion (e.g. 250) has a substantially planar bottom surface, fig. 4.
Tsai and Kamineni do not expressly teach a convex top surface.
Patil further teaches:
(see fig. 1f) wherein the first horizontal portion (e.g. of 117) has a convex top surface. See Patil at col 5, ln 40–65.
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Tsai and Kamineni with the teachings of Patil because a convex to surface (e.g. bump) can protect underlying metal layers. See Patil at col 5, ln 40–65.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsai in view of Kamineni, as applied to claim 11 above, in further view of Hou et al., US Publication No. 2017/0170027 A1.
Regarding claim 13:
Tsai and Kamineni teach all the limitations of claim 11 above, but do not expressly teach:
wherein the forming of the gate dielectric layer comprises:
deposing a high-k dielectric layer;
forming a layer comprising TiSiN on the high-k dielectric layer;
performing an annealing process after the forming of the layer comprising TiSiN;
forming a layer comprising silicon over the high-k dielectric layer;
performing an annealing process after the forming of the layer comprising silicon; and
selectively removing the layer comprising silicon and the layer comprising TiSiN.
In an analogous art, Hou teaches (see figs. 5-6):
wherein the forming of the gate dielectric layer comprises:
deposing a high-k dielectric layer (HK);
forming a layer comprising TiSiN (TSN) on the high-k dielectric layer;
performing an annealing process (e.g. anneal at para. [0021]) after the forming of the layer comprising TiSiN;
forming a layer comprising silicon (e.g. capping layer, see silicon at para. [0035]) over the high-k dielectric layer;
performing an annealing process (e.g. anneal to drive in atoms at para. [0021]) after the forming of the layer comprising silicon; and
selectively removing the layer comprising silicon (e.g. capping layer is removed at para. [0043]) and the layer comprising TiSiN (TSN) (e.g. See para. [0043] disclosing “However, in some embodiments and as shown in FIG. 5D, at least a portion of the conformal fluorinated barrier metal layer 508A may remain (e.g., after the PCA process 514),…” Because the disclosure indicates “at least a portion…remains”, this means a portion of the TSN layer 508A is etched during the removal of the capping layer. This etching of TSN layer 508A discloses the limitation “selectively removing” recited in the claim.)
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Tsai with the teachings of Hou because the process has the advantage of “…passivating interfacial and/or bulk defects for each of the interfacial layer 110 and the gate dielectric layer 112” See Hou at para. [0021].
Claim(s) 18 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hou, as applied to claim 17 above, in view of Kamineni et al., US Publication No. 2018/0174965 A1.
Regarding claim 18 Hou teaches all the limitations of claim 17 above, and further teaches the metal layer can comprise cobalt at para. [0020].
In an analogous art, Kamineni teaches:
18. The method of claim 17, wherein the forming of the metal layer comprises (see figs. 1-11):
performing a first deposition process to form a first sublayer (232, e.g. RFPVD at para. [0029]);
performing a second deposition process to form a second sublayer (250, e.g. CVD at para. [0032]) over the first sublayer, wherein the second deposition process differs from the first deposition process; and
performing a third deposition process to form a third sublayer (e.g. electrochemical plating of Co to fill the trench at para. [0023]) over the second sublayer to fill the trench, wherein the third deposition process differs from the first deposition process and the second deposition process.
Kamineni further teaches:
19. The method of claim 18, wherein the first deposition process comprises a directional physical vapor deposition (PVD) process (232, e.g. RFPVD at para. [0029]), and the first sublayer has a non-uniform thickness (e.g. In fig. 3A, layer 232 has non-uniform thickness along top horizontal surface of 204.)
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Hou with the teachings of Kamenini because “Advantageously, the integrated circuit device fabrication processes disclosed herein provide for semiconductor devices having substantially void-free gap fill…” See Kamenini at para. [0021], also see para. [0003].
Claim(s) 18 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hou, as applied to claim 17 above, in view of Kamineni et al., US Publication No. 2018/0174965 A1.
Regarding claim 18 Hou teaches all the limitations of claim 17 above, and further teaches the metal layer can comprise cobalt at para. [0020].
In an analogous art, Kamineni teaches:
18. The method of claim 17, wherein the forming of the metal layer comprises (see figs. 1-11):
performing a first deposition process to form a first sublayer (232, e.g. RFPVD at para. [0029]);
performing a second deposition process to form a second sublayer (“A layer of second semiconductor material (not shown) may be deposited to form, for example, a barrier layer or an adhesion layer”. The layer of second semiconductor material is formed by ALD at para. [0032].) over the first sublayer, wherein the second deposition process differs from the first deposition process; and
performing a third deposition process to form a third sublayer (250, e.g. CVD at para. [0032]; and/or electrochemical plating of Co to fill the trench at para. [0023]) over the second sublayer to fill the trench, wherein the third deposition process differs from the first deposition process and the second deposition process.
Kamineni further teaches:
20. The method of claim 18, wherein a portion of the second sublayer (“A layer of second semiconductor material at para. [0032] is disposed directly under a portion of the first sublayer (232) (In fig. 3A, the layer of second semiconductor material is formed on layer 232. “As shown in FIG. 3B, the first semiconductor material layer and the second layer of semiconductor material together may form semiconductor material layer 230”, para. [0030]. The layer of second semiconductor material is formed directly under a portion of the first sublayer 232 located along top horizontal surface of 204.)
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Hou with the teachings of Kamenini because “Advantageously, the integrated circuit device fabrication processes disclosed herein provide for semiconductor devices having substantially void-free gap fill…” See Kamenini at para. [0021], also see para. [0003].
Conclusion
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/Michele Fan/
Primary Examiner, Art Unit 2818
29 December 2025