DETAILED ACTION
This correspondence is in response to the communications received May 24, 2024. Claims 1-20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
It appears that all claims are directed to the embodiment captured in the sequence of formation as can be seen in Figs. 42A-46A.
Applicant’s Claim to Figure Comparison
It is noted that this comparison is merely for the benefit of reviewers of this office action during prosecution, to allow for an understanding of the examiner’s interpretation of the Applicant’s independent claims as compared to disclosed embodiments in Applicant’s Figures. No response or comments are necessary from Applicant.
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Regarding claim 1, the Applicant discloses in Figs. 42A-46A, a structure, comprising:
an active region (110A);
a gate (140A) located over the active region in a cross-sectional side view (140A over 110A)
a gate helmet structure (550A) located over the gate in the cross-sectional side view (550A is over 140A),
wherein the gate helmet structure (550A) contains a dielectric material (¶ 0125); and
a liner (510A) disposed between the gate helmet structure and the gate in the cross-sectional side view (between 550A and 140A),
wherein the liner (510A) and the gate helmet structure (550A) have different material compositions (¶ 0125),
wherein segments of the liner layer are also located on side surfaces of the gate helmet structure in the cross-sectional side view (many segments of 510A on side surfaces of 550A).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (US 2016/0043186) in view of Park et al. (US 2014/0327062).
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Regarding claim 1, the prior art of Liu discloses in Fig. 4, a structure, comprising:
an active region (The ‘active region’ is the general localized region of the semiconductor substrate where the source, drain and channel are formed. So here, the portion of “semiconductor substrate 101”, ¶ 0012, immediately under “gate dielectric layer 122”, ¶ 0027, which is the channel and where the source and drain regions are formed, hereinafter referred to as ‘AR’. The exact phrase of “active region” is not disclosed by Liu however, which will be treated in the subsequent combination rejection below.);
a gate (“gate electrode 126g”, ¶ 0041) located over the active region in a cross-sectional side view (126g over AR in cross section view of figures above);
a gate helmet structure (combination of portions of “etch stop layer 140”, ¶ 0049, and “second layer 132b and the etch stop layer 140 are formed of the same material”, ¶ 0075, immediately over 126g and between “contact plugs 192”, ¶ 0066, hereinafter referred to as ‘GHS’) located over the gate in the cross-sectional side view (GHS over 126g),
wherein the gate helmet structure contains a dielectric material (GHS which is 140, is formed of, “The etch stop layer 140 is made of silicon nitride”, ¶ 0049); and
a liner (“first layer 131b conformally covers the insulating layer 120 and the inner walls W and the bottom surface B of the recess R”, ¶ 0073) disposed between the gate helmet structure and the gate in the cross-sectional side view (131b is formed between GHS and 126g),
wherein the liner and the gate helmet structure have different material compositions (liner/131b is the material of, “layer 131b includes metal oxide”, ¶ 0075, and GHS/140/132b are the materials of, “The etch stop layer 140 is made of silicon nitride”, ¶ 0049, “second layer 132b and the etch stop layer 140 are formed of the same material”, ¶ 0075),
wherein segments of the liner layer (vertical segments of 131b) are also located on side surfaces of the gate helmet structure in the cross-sectional side view (vertical side surfaces of portion 132b of GHS, have vertical segments of 131b thereon).
Liu does not explicitly state that the region of the semiconductor substrate where the source, drain and channel are formed, is “an active region”.
Park discloses in ¶ 0022, the general layout of a transistor which includes, “The substrate may include a semiconductor active region having a channel region between first and second source/drain regions, and the oxide dielectric layer may be on the channel region between the channel region and the electrode.”
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of, the region of the semiconductor substrate where the source, drain and channel are formed, is “an active region”, as disclosed by Park in the system of Liu, for the purpose of providing an active semiconductor region which allows for the formation of source, drain and channel so as to include the necessary components of a functioning transistor. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 11, the prior art of Lin et al. disclose the structure of claim 1, and Lin discloses in Fig. 4, wherein the gate helmet structure has a profile that resembles a letter ?T? in the cross-sectional side view (combination of portions of “etch stop layer 140”, ¶ 0049, and “second layer 132b and the etch stop layer 140 are formed of the same material”, ¶ 0075, immediately over 126g and between “contact plugs 192”, ¶ 0066. Where noted portions are formed in the shape of a ‘T’ as can be seen in Fig. 4).
Claims 12 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (US 2016/0043186) in view of Park et al. (US 2014/0327062) in view of Doris et al. (US 2017/0092765).
Regarding claim 12, the prior art of Lin et al. disclose the structure of claim 1, however Lin fails to disclose, “wherein a thickness of the liner is in a range between about 0.5 nanometers and about 5 nanometers.”
Doris teaches a gate cap dielectric (“gate cap portion 18 may include a hard mask material such as, for example, silicon dioxide”, ¶ 0043) with a thickness in the range of 5-20 nm (“gate cap portion 18 can have a thickness from 5 nm to 20 nm”, ¶ 0043). In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990)
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of, “wherein a thickness of the liner is in a range between about 0.5 nanometers and about 5 nanometers”, as disclosed by Doris in the system of Liu, for the purpose of providing a diminutive dimension for a gate protection layer which is of a similar size to a modern gate electrode for the purpose of increasing device density put unit area. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 16, the prior art of Lin et al. disclose the structure of claim 14, however Lin fails to disclose, “wherein the liner has a greater dielectric constant than the first dielectric component.”
Doris teaches the equivalent “liner” (“The ILD material 26 may be composed of, for example, silicon dioxide, undoped silicate glass (USG), fluorosilicate glass (FSG), borophosphosilicate glass (BPSG), a spin-on low-k dielectric layer, a chemical vapor deposition (CVD) low-k dielectric layer or any combination thereof. The term “low-k” as used throughout the present application denotes a dielectric material that has a dielectric constant of less than silicon dioxide. In one embodiment, the ILD material 26 can be formed utilizing a deposition process including, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), evaporation or spin-on coating.”, ¶ 0055) has a low dielectric constant, and an equivalent “first dielectric component” has a relatively higher dielectric constant (“gate cap portion 18 may include a hard mask material such as, for example, silicon dioxide”, ¶ 0043). Where low-k is understood to mean a dielectric constant (from above teaching) lower than silicon oxide which is around 4, which is lower than silicon nitride’s dielectric constant of around 7. See Horiuchi et al. (US 2007/0212843) Table 1, below, which discloses these physical quantities associated with materials.
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Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of, “wherein the liner has a greater dielectric constant than the first dielectric component”, as disclosed by Doris in the system of Liu, for the purpose of providing a gate protection layer that protects the gate structure during subsequent BEOL structure formation, while using lower k materials higher up in the BEOL so as to not allow for capacitive build up. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Double Patenting
An analysis was conducted with regard to the availability of the parent applications for use in non-statutory double patenting rejections, see below.
1.) 18365315, now Su et al. (US 12,237,418)
For instant application’s claims 1 and 13, this reference does not cite any liner element, and is therefore not relevant in a non-statutory double patenting rejection.
For instant application’s claim 18, this reference does not teach that the third dielectric layer has a dielectric constant greater than the second dielectric layer’s dielectric constant.
2.) 17322267, now Su et al. (US 11,996,481)
This reference has all claims directed to method claims, and is therefore not relevant in a non-statutory double patenting rejection.
3.) 16510554, now Su et al. (US 11,011,625)
For instant application’s claim 1, it is required to have “wherein the liner and the gate helmet structure have different material compositions”. However, the material composition of the liner is never stated in the claims of the ‘625 patent.
For instant application’s claim 13, a non-statutory double patenting rejection has been made below.
For instant application’s claim 18, it is required to have first through third dielectric layers with increasing dielectric constant from first to third, which is not disclosed in the claims of the ‘625 patent claim set.
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 13 and 14 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 4-6 of U.S. Patent No. 11,011,625. Although the claims at issue are not identical, they are not patentably distinct from each other because the parent application contains each of the instant application’s claimed limitations.
Note, in the following analysis, the bolded capital letters indicate the matching limitations in the claims being compared.
Claim limitation(s) of the instant application.
Claim limitation(s) of the ‘625 patent
13. A structure, comprising:
A an active region;
B a gate located over the active region in a cross-sectional side view;
C a gate spacer structure located laterally adjacent to the gate in the cross-sectional side view;
D an interlayer dielectric (ILD), wherein the gate spacer structure is located between the ILD and the gate in the cross-sectional side view; and
E a dielectric liner;
wherein:
E1 a first segment of the liner is located over an upper surface of the gate in the cross-sectional side view;
E2 a second segment of the liner is located on a portion, but not all, of a side surface of the gate spacer structure in the cross-sectional side view;
E3 a third segment of the liner is located over an upper surface of the gate spacer structure in the cross-sectional side view; and
E4 a fourth segment of the liner is located on a portion, but not all, of a side surface of the ILD in the cross-sectional side view.
1. A semiconductor device, comprising:
A a semiconductor layer;
B a gate structure disposed over the semiconductor layer;
D an interlayer dielectric (ILD) layer;
C a spacer disposed between the gate structure and the ILD layer,
wherein a height of the spacer is greater than a height of the gate structure but less than a height of the ILD layer; and
E a liner E1 disposed on the gate structure and E2 on the spacer and E4 on a portion of a sidewall of the ILD layer,
wherein the spacer and the liner have different material compositions;
wherein:
the gate structure is disposed on a sidewall of a first portion of the spacer; and
E2 the liner is disposed on a sidewall of a second portion of the spacer, wherein the second portion is disposed above the first portion.
4. The semiconductor device of claim 1, E3 wherein the liner is further disposed on a top surface of the spacer.
14. The structure of claim 13, further comprising:
A a first dielectric component located over at least the first segment and the second segment of the liner in the cross-sectional side view; and
B a second dielectric component located over the first dielectric component in the cross-sectional side view,
C wherein the second dielectric component has a greater dielectric constant than the first dielectric component.
5. The semiconductor device of claim 1, further comprising: a dielectric structure disposed over the liner, wherein the dielectric structure contains a dielectric material having a dielectric constant greater than about 4, and wherein the dielectric structure has a T-shaped profile in a cross-sectional view.
6. The semiconductor device of claim 5, wherein:
the dielectric structure includes a A first portion and a B second portion disposed over the first portion; and
C a dielectric constant of the second portion is greater than a dielectric constant of the first portion.
15. The structure of claim 14, wherein a bottom-facing surface of the second dielectric component is wider than a bottom-facing surface of the first dielectric component in the cross-sectional side view.
This limitation not present in the claims of ‘625 patent.
16. The structure of claim 14, wherein the liner has a greater dielectric constant than the first dielectric component.
This limitation not present in the claims of ‘625 patent.
17. The structure of claim 13, wherein:
the third segment of the liner layer is more elevated vertically than the first segment of the liner layer in the cross-sectional side view; and
the fourth segment of the liner layer is more elevated vertically than the second segment of the liner layer in the cross-sectional side view.
This limitation not present in the claims of ‘625 patent.
Allowable Subject Matter
Claims 2-10, 15 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 2 is objected to due Liu et al. (US 2016/0043186) fails to teach where first portion of the gate helmet has a lower dielectric constant than the second portion of the gate helmet. This is because Liu teaches wherein both portions are the same material (“The etch stop layer 140 is made of silicon nitride”, ¶ 0049, “second layer 132b and the etch stop layer 140 are formed of the same material”, ¶ 0075). Therefore, Liu does not disclose, “the second dielectric constant is greater than the first dielectric constant.”
Claims 3-10 are objected to, due to their dependence upon claim 2.
Claim 15 is objected to due Liu et al. (US 2016/0043186) fails to teach the geometric relationship between the first dielectric and the second dielectric components, as claimed, “wherein a bottom-facing surface of the second dielectric component is wider than a bottom-facing surface of the first dielectric component in the cross-sectional side view.”
Claim 17 is objected to due Liu et al. (US 2016/0043186) fails to teach the relative orientation of the first segment, second segment and fourth segment to each other, as claimed, “the third segment of the liner layer is more elevated vertically than the first segment of the liner layer in the cross-sectional side view; and the fourth segment of the liner layer is more elevated vertically than the second segment of the liner layer in the cross-sectional side view.”
Claims 13-20 are allowed.
Regarding claim 13, the prior art of Liu et al. (US 2016/0043186) discloses in Fig. 4, a structure of a transistor, but fails to disclose the specific characteristic recited in the claims of the instant invention e.g. the combination of claim features of active region, gate, gate spacer, interlayer dielectric (ILD), liner and the relative orientation of the liner to the surrounding features, as detailed in the limitations,
“a first segment of the liner is located over an upper surface of the gate in the cross-sectional side view;
a second segment of the liner is located on a portion, but not all, of a side surface of the gate spacer structure in the cross-sectional side view;
a third segment of the liner is located over an upper surface of the gate spacer structure in the cross-sectional side view; and
a fourth segment of the liner is located on a portion, but not all, of a side surface of the ILD in the cross-sectional side view.”
Claims 14-17 have been allowed due to their dependence upon claim 13.
Regarding claim 18, the prior art of Liu et al. (US 2016/0043186) discloses in Fig. 4, a structure of a transistor, but fails to disclose the specific characteristic recited in the claims of the instant invention e.g. the combination of claim features of a gate, first dielectric layer, second dielectric layer and third dielectric layer, and the relationships of dielectric constants as detailed in the limitations,
“wherein the second dielectric layer has a second dielectric constant greater than the first dielectric constant; and
a third dielectric layer located over the second dielectric layer in the cross-sectional side view,
wherein the third dielectric layer has a third dielectric constant greater than the second dielectric constant.”
Claims 19 and 20 have been allowed due to their dependence upon claim 18.
Further, Wang et al. (US 2020/0168729) Fig. 13, shown below, shows a multi stack of dielectric layers over a gate, however their dielectric constants are not in the configuration as claimed.
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Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Eduardo A Rodela whose telephone number is (571)272-8797. The examiner can normally be reached M-F, 8:30-5:00pm ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara B Green can be reached on (571) 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EDUARDO A RODELA/Primary Examiner, Art Unit 2893
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