DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1,5, 6, 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chiang et al. ( US-20050093143-A1; Chiang) in view of JP (JP-3943352-B2;JP).
Regarding claim 1, Chiang discloses a semiconductor module, comprising: a carrier (Fig. 2B-2C,110;¶28); a plurality of passive components (Fig. 2B-2C, 130 ;¶28) disposed over the carrier; an electronic component (Fig. 2B-2C, 120 ;¶28 EEPROM) disposed over the carrier and …; and an encapsulation layer (Fig. 2B-2C, 150;¶29) covering and contacting the plurality of passive components and the electronic component.
Chiang is silent on the electronic component configured to clamp a voltage of the semiconductor module.
JP discloses an electronic component (Fig. 4, EEPROM; ¶3)
configured with voltage clamping circuit (Fig. 4, 44; ¶4)
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to configure the electronic component with a voltage clamping circuit to clamp the boosted power supply voltage generated to a desired level.
Regarding claim 5, Chiang in view of JP discloses the semiconductor module of Claim 1, wherein the encapsulation layer (Fig. 2B-2C, 150;¶29) has a first top surface higher than a second top surface of the passive components (Fig. 2B-2C, 130 ;¶28) and a third top surface of the electronic component (Fig. 2B-2C, 120 ;¶28 EEPROM).
Regarding claim 6, Chiang in view of JP discloses the semiconductor module of Claim 1, wherein the passive components (Fig. 2B-2C, 130 ;¶28 Chiang) comprise a resistor (¶5) and a capacitor.(¶5)
Chiang discloses in paragraph 5 that the passive components in a conventional MMC package is a resistor and a capacitor. Therefore it is reasonable to view the disclosed passive components of the embodiments to also be resistor and capacitors.
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art for the passive devices to be resistors and capacitors for impedance matching.
Regarding claim 10, Chiang in view of JP discloses the semiconductor module of Claim 1, further comprising a shield (Fig. 2D, 160 ;¶30 Chiang) covering the encapsulation layer. (Fig. 2D, 150 ;¶29 Chiang)
Claim(s) 2-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chiang et al. ( US-20050093143-A1; Chiang) in view of JP (JP-3943352-B2;JP), and further in view of Han et al. (US-20220013472-A1; Han) .
Regarding claim 2, Chiang in view of JP discloses the semiconductor module of Claim 1, but is silent on wherein the passive components comprise a first passive component and a second passive component, wherein a first axis of the first passive component and a second axis of the second passive component are not parallel to each other.
Han discloses an encapsulated semiconductor module comprising a plurality of passive components (Fig. 3, 312; ¶31) and an electronic component (Fig. 3, 304; ¶31 memory), where the a first axis (Fig. 3, a first 312 defined by 314; ¶31) of the first passive component and a second axis (Fig. 3, a second 312 defined by 318; ¶31) of the second passive component are not parallel (perpendicular) to each other.
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to configure the passive devices perpendicular to each other for providing a shielding of the electronic component.
Regarding claim 3, Chiang in view of JP and Han discloses the semiconductor module of Claim 2, wherein the passive components (Fig. 3, 312; ¶31) comprise a third passive component (Fig. 3, a third 312 defined by 314; ¶31 Han), wherein a third axis of the third passive component is parallel to the first axis. (Fig. 3, a first 312 defined by 314; ¶31 Han)
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to configure the passive devices perpendicular to each other for providing a shielding of the electronic component.
Regarding claim 4, Chiang in view of JP discloses the semiconductor module of Claim 1, but is silent on further comprising a shield disposed between the passive components and the electronic component.
Han discloses an encapsulated semiconductor module comprising a plurality of passive components (Fig. 7, 312 between 306 and 308; ¶31) and an electronic component (Fig. 7, 304; ¶31 memory), where a shield (Fig. 7, at least one 312 between 304 and 306; ¶39) disposed between the passive components and the electronic component.
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to configure the passive devices perpendicular to each other for providing a shielding of the electronic component.
Regarding claim 9, Chiang in view of JP discloses the semiconductor module of Claim 6, but is silent on wherein the capacitor is disposed over the resistor, and a first elevation of a top surface of the capacitor is higher than or substantially the same as a second elevation of a top surface of the electronic component with respect to the carrier.
Han discloses a package comprising a stack of passive devices (Fig. 12, 312A/312B; ¶45) and a semiconductor component (Fig. 12, 304; ¶42) disposed on a carrier (Fig. 12, 302; ¶45), where the top passive device is higher than a top surface of the semiconductor component.
Han does not specifically disclose which passive element is on top of the stack. However there are only two choices available that one of ordinary skill in the art would capable of choosing to enhance package functionality.
Before the effective filing date it would have been obvious to one having ordinary skill in the art to form the capacitor of the resistor in a stacked configuration to allow more space on the carrier for forming a high density package.
. Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chiang et al. ( US-20050093143-A1; Chiang) in view of JP (JP-3943352-B2;JP), and further in view of Yang et al. (US-20200373289-A1; Yang) .
Regarding claim 7, Chiang in view of JP discloses the semiconductor module of Claim 6, but is silent on wherein the electronic component comprises a terminal connected to a terminal of the resistor.
Yang discloses a package comprising a semiconductor component (Fig. 4b, 104; ¶53) terminal (Fig. 4b, 114; ¶53) connected to a resistor terminal. (Fig. 4b, 162; ¶53)
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to connect the semiconductor component to the resistor for enhanced electrical functionality.
Regarding claim 8, Chiang in view of JP and Yang discloses the semiconductor module of Claim 7, wherein the encapsulation layer (Fig. 4b, 256; ¶54) vertically, with respect to the carrier (Fig. 4b, 196; ¶50), covers an electrical transmission path connecting the terminal (Fig. 4b, 114; ¶53) of the electronic component and the terminal of the resistor. (Fig. 4b, 162; ¶53)
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to cover the package with encapsulant to protect the components from damage.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chiang et al. ( US-20050093143-A1; Chiang) in view of JP (JP-3943352-B2;JP), and further in view of Ramachandran et al. (US-20140327105-A1; Ramachandran) .
Regarding claim 11, Chiang in view of JP discloses the semiconductor module of Claim 1, but is silent on wherein the electronic component comprises an electrostatic discharge (ESD) device.
Ramachandran discloses a package comprising a semiconductor component (Fig. 13, 1332/1310; ¶58) connected to an ESD diode. (Fig. 13, 1348; ¶59)
Before the effective filing date of the invention it would have been obvious to one of ordinary skill in the art to combine an ESD component with the semiconductor component to protect the device from voltage spikes caused by electrostatic discharge.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yang et al. (US-20200373289-A1; Yang).
Regarding claim 13, Yang discloses a semiconductor module, comprising: a carrier (Fig. 2b, 150; ¶41) comprising a first wiring structure (Fig. 2b, 154b left of hole 160; ¶38) and a second wiring structure (Fig. 2b, 154b right of hole 160; ¶38); a first device (Fig. 2c, 162 left of hole 160; ¶43) electrically connected to the first wiring structure, wherein the first device and the first wiring structure collectively define a first group (left group); and a second device (Fig. 2c, 162 right of 160; ¶43) electrically connected to the second wiring structure, wherein the second device and the second wiring structure collectively define a second group (right group), wherein the first group operates independent of the second group.
Regarding claim 14, Yang discloses the semiconductor module of Claim 13, wherein the first wiring structure (Fig. 2b, 154b left of hole 160; ¶38) is free from being electrically connected to the second device (Fig. 2c, 162 right of 160; ¶43), and the second wiring structure (Fig. 2b, 154b right of hole 160; ¶38) is free from being electrically connected to the first device. (Fig. 2c, 162 left of hole 160; ¶43)
Regarding claim 15, Yang discloses the semiconductor module of Claim 13, wherein the first group (left group) is configured to process a first signal transmitted from a first external (external to the group) electronic component (Fig. 4a, 200; ¶43) to a second external (external to the group) electronic component (Fig. 4a, 104; ¶43), and the second group (right group) is configured to process a second signal transmitted from the second external electronic (Fig. 4a, 104; ¶43) component to the first external electronic component. (Fig. 4a, 200; ¶43)
Regarding claim 17, Matsuda discloses an electronic system (Fig. 1/2, 3; ¶16), comprising: a plurality of passive components (Fig. 5, 40; ¶7) ; a first electronic component (Fig. 5, 44; ¶6) configured to clamp a voltage of the electronic system and having a first terminal (not labeled) ; and an encapsulation layer (Fig. 1/2, 8; ¶49) covering and contacting the plurality of passive components and the first electronic component; and a second electronic component (Fig. 4, 45; ¶16) electrically connected to the first terminal.
Regarding claim 18, Matsuda discloses electronic system of Claim 17, further comprising a third electronic component (Fig. 5, transistors of 40; ¶7) electrically connected to a terminal of the passive components. (Fig. 5, capacitors of 40; ¶7)
Allowable Subject Matter
Claims 12, 16,19,20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance, which paraphrases and summarizes the claimed invention without intending to be limiting, wherein the legally defined scope of the claimed invention is defined by the allowed claims themselves in view of the written description under 35 USC 112. This statement is not intended to necessarily state all the reasons for allowance or all the details why the claims are allowed and has not been written to specifically or impliedly state that all the reasons for allowance are set forth (MPEP 1302.14).
The relevant art discloses passive components separate from EOS circuitry, shield material, and voltage clamping circuitry but is silent on the limitations cited below in combination with the rest of the claimed limitations.
Regarding claim 12, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, the instant invention regarding: " wherein the passive components comprise an electrical overstress (EOS) circuit.”, as recited in Claim 12, with the remaining features.
Regarding claim 16, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, the instant invention regarding: " further comprising a shield disposed in the carrier and between the first wiring structure and the second wiring structure.”, as recited in Claim 16, with the remaining features.
Regarding claim 19, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, the instant invention regarding: " and a second signal transmitted from the device to the third electronic component.”, as recited in Claim 19, with the remaining features.
Regarding claim 20, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, the instant invention regarding: " wherein the first electronic component is configured to block a signal from the third electronic component to the second electronic component when a voltage difference between the first terminal and a second terminal of the electronic component exceeds a predetermined value, wherein the signal is transmitted through the passive components and the first electronic component.”, as recited in Claim 20, with the remaining features.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
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/LAWRENCE C TYNES JR./Examiner, Art Unit 2899
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