DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 11 is objected to because of the following informalities: the text “210” in line 6 is suggested to be deleted.
Claim 13 is objected to because of the following informalities: the word “wherein” in line 2 is suggested to be deleted.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 10 and 17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 10 recites the limitation "the first dry etching variation" in line 2. There is insufficient antecedent basis for this limitation in the claim.
Claim 17 recites the limitation "the first dry etching variation" in lines 2-3. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-2 and 4-8 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2021/0233809) in view of Chang (US 2019/0148287).
Regarding claim 1, Lee discloses, in FIG. 1 and in related text, a method of forming a semiconductor device, comprising:
providing a substrate layer (110, 100) including a metal interconnect feature (130) embedded in the substrate layer (see Lee, FIG. 1, [0020]);
depositing a liner layer (500) on the metal interconnect feature (see Lee, FIG. 5, [0034]);
depositing an etching stop layer (600) on the liner layer and the semiconductor substrate layer (see Lee, FIG. 6, [0035]);
forming a dielectric layer (700) on the etching stop layer with a via trench (for conductive feature 730) to expose the etching stop layer; etching the etching stop layer and the liner layer to form a via structure (730) to expose the metal interconnect feature (see Lee, FIG. 7, [0036]).
Lee discloses the substrate layer including devices and interconnects (see Lee, [0022]). Lee does not explicitly disclose a semiconductor substrate layer.
Chang teaches a semiconductor substrate layer including devices and interconnects (see Chang, [0014]-[0017]).
Lee does not explicitly disclose wherein the via structure has an hourglass-shaped profile.
Chang teaches wherein the via structure (in via hole 212) has an hourglass-shaped profile (see Chang, FIG. 2A, [0020]-[0022]).
Lee and Chang are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lee with the features of Chang because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Lee to include a semiconductor substrate layer, wherein the via structure has an hourglass-shaped profile, as taught by Chang, because it is simple substitution of one known element for another to obtain predictable results (as substrate layer for semiconductor devices) (see MPEP § 2143), and to reduce via resistance and increase mechanical strength of via landing (see Chang, [0040]).
Regarding claim 2, Lee in view of Chang teaches the method of claim 1.
Lee discloses the metal interconnect feature (see discussion on claim 1 above).
Chang teaches wherein: the interconnect feature (206) extends in a first direction (into FIG. 2A), and the via structure (in via hole 212) has an enlarged (compared to W1) bottom critical dimension (W4) along a second direction (horizontal direction in FIG. 2A), wherein the first direction is perpendicular to the first direction (see Lee, FIG. 2A, [0024]), with the same analogous prior art and field of endeavor statement and the same motivation as provided for in claim 1.
Regarding claim 4, Lee in view of Chang teaches the method of claim 1.
Chang teaches wherein: the etching stop layer is an aluminum-based etching stop layer (see Chang, [0020]), with the same analogous prior art and field of endeavor statement and the same motivation as provided for in claim 1.
Regarding claim 5, Lee in view of Chang teaches the method of claim 1.
Lee discloses wherein: the liner layer (capping layer 500) is a cobalt (Co) layer, and a thickness of the cobalt layer is in a range from 0.5 nm to 3 nm (see Lee, [0032], [0034]).
Regarding claim 6, Lee in view of Chang teaches the method of claim 1.
Lee discloses wherein: the substrate layer further comprises a barrier layer (170) and a substrate (110), wherein the barrier layer is formed between the metal interconnect feature (copper metal 160 of conductive feature 130) and the substrate (see Lee, FIG. 1, [0020]).
Chang teaches the semiconductor substrate layer (see discussion on claim 1 above), with the same analogous prior art and field of endeavor statement and the same motivation as provided for in claim 1.
Regarding claim 7, Lee in view of Chang teaches the method of claim 1.
Chang teaches wherein:
the hourglass-shaped profile has a waist plane (at interface between dielectric layer 210 and etch stop layer 208),
a distance between the waist plane and a top surface of the dielectric layer is a first distance (H2 – H1 = 20 nm),
a distance between the waist plane and a top surface of the metal interconnect feature is a second distance (H1 = 1 nm), and
a ratio (20/1 = 20) between the first distance and the second distance is in a range from 2.67 to 50 (see Chang, FIG. 2A, [0021]), with the same analogous prior art and field of endeavor statement and the same motivation as provided for in claim 1.
Regarding claim 8, Lee in view of Chang teaches the method of claim 1.
Chang teaches wherein: the first distance is in a range from 16 nm to 50 nm, and
the second distance is in a range from 1 nm to 6 nm (see discussion on claim 7 above), with the same analogous prior art and field of endeavor statement and the same motivation as provided for in claim 1.
Claims 12-15 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2021/0233809) in view of Chang (US 2019/0148287).
Regarding claim 12, Lee discloses, in FIG. 1 and in related text, a method of forming a semiconductor device, comprising:
providing a substrate layer (110, 100) including a metal interconnect feature (130) embedded in the substrate layer (see Lee, FIG. 1, [0020]);
depositing a liner layer (500) on the metal interconnect feature (see Lee, FIG. 5, [0034]);
depositing an etching stop layer (600) on the liner layer and the substrate layer, wherein the etching stop layer has a step structure at an edge of the liner layer (see Lee, FIG. 6, [0035]);
forming a dielectric layer (700) on the etching stop layer with a via trench (for conductive feature 730) to expose the etching stop layer; etching the etching stop layer and the liner layer to form a via structure (730) to expose the metal interconnect feature (see Lee, FIG. 7, [0036]).
Lee discloses the substrate layer including devices and interconnects (see Lee, [0022]). Lee does not explicitly disclose a semiconductor substrate layer.
Chang teaches a semiconductor substrate layer including devices and interconnects (see Chang, [0014]-[0017]).
Lee and Chang are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lee with the features of Chang because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Lee to include a semiconductor substrate layer, as taught by Chang, because it is simple substitution of one known element for another to obtain predictable results (as substrate layer for semiconductor devices) (see MPEP § 2143).
Regarding claim 13, Lee in view of Chang teaches the method of claim 12.
Chang teaches wherein: wherein the via structure (in via hole 212) has an hourglass-shaped profile (see Chang, FIG. 2A, [0020]-[0022]), with at least the same analogous prior art and field of endeavor statement and the same motivation as provided for in claim 12, and to reduce via resistance and increase mechanical strength of via landing (see Chang, [0040]).
Regarding claim 14, Lee in view of Chang teaches the method of claim 12.
Chang teaches wherein:
the hourglass-shaped profile has a waist plane (at interface between dielectric layer 210 and etch stop layer 208),
a distance between the waist plane and a top surface of the dielectric layer is a first distance (H2 – H1 = 20 nm),
a distance between the waist plane and a top surface of the metal interconnect feature is a second distance (H1 = 1 nm), and
a ratio (20/1 = 20) between the first distance and the second distance is in a range from 2.67 to 50 (see Chang, FIG. 2A, [0021]), with the same analogous prior art and field of endeavor statement and the same motivation as provided for in claim 13.
Regarding claim 15, Lee in view of Chang teaches the method of claim 14.
Chang teaches wherein: the first distance is in a range from 16 nm to 50 nm, and the second distance is in a range from 1 nm to 6 nm (see discussion on claim 14 above), with the same analogous prior art and field of endeavor statement and the same motivation as provided for in claim 14.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Kahlert (US 2010/0078821).
Regarding claim 18, Kahlert discloses, in FIG. 1a and in related text, a semiconductor device, comprising:
a semiconductor substrate layer (101, 110) including a metal interconnect feature (112) embedded in the semiconductor substrate layer;
a liner layer (113) on the metal interconnect feature;
an etching stop layer (114) on the liner layer and the semiconductor substrate layer;
a dielectric layer (121) on the etching stop layer; and
a via structure (opening 121A) through the dielectric layer, the etching stop layer, and the liner layer exposing the metal interconnect feature (see Kahlert, [0011], [0043]).
Kahlert discloses the via structure (opening 212A) having a straight sidewalls (see Kahlert, FIG. 1a).
Kahlert does not explicitly disclose the via structure having an hourglass-shaped sidewalls. Kahlert does not explicitly disclose wherein the via structure has an hourglass-shaped profile.
However, the limitation is mere changes in shape and would have been found obvious absent persuasive evidence that the particular configuration of the claim was significant. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). See also, MPEP § 2144.04.
Claims 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2021/0233809) in view of Chang (US 2019/0148287).
Regarding claim 18, Lee discloses, in FIG. 7 and in related text, a semiconductor device, comprising:
a substrate layer (110, 100) including a metal interconnect feature (130) embedded in the substrate layer;
a liner layer (500) on the metal interconnect feature;
an etching stop layer (600) on the liner layer and the semiconductor substrate layer;
a dielectric layer (700) on the etching stop layer; and
a via structure (730) through the dielectric layer, the etching stop layer, and the liner layer exposing the metal interconnect feature (see Lee, [0020], [0034]-[0036]).
Lee discloses the substrate layer including devices and interconnects (see Lee, [0022]). Lee does not explicitly disclose a semiconductor substrate layer.
Chang teaches a semiconductor substrate layer including devices and interconnects (see Chang, [0014]-[0017]).
Lee does not explicitly disclose wherein the via structure has an hourglass-shaped profile.
Chang teaches wherein the via structure (in via hole 212) has an hourglass-shaped profile (see Chang, FIG. 2A, [0020]-[0022]).
Lee and Chang are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lee with the features of Chang because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Lee to include a semiconductor substrate layer, wherein the via structure has an hourglass-shaped profile, as taught by Chang, because it is simple substitution of one known element for another to obtain predictable results (as substrate layer for semiconductor devices) (see MPEP § 2143), and to reduce via resistance and increase mechanical strength of via landing (see Chang, [0040]).
Regarding claim 19, Lee in view of Chang teaches the device of claim 18.
Chang teaches wherein:
the hourglass-shaped profile has a waist plane (at interface between dielectric layer 210 and etch stop layer 208),
a distance between the waist plane and a top surface of the dielectric layer is a first distance (H2 – H1 = 20 nm),
a distance between the waist plane and a top surface of the metal interconnect feature is a second distance (H1 = 1 nm), and
a ratio (20/1 = 20) between the first distance and the second distance is in a range from 2.67 to 50 (see Chang, FIG. 2A, [0021]), with the same analogous prior art and field of endeavor statement and the same motivation as provided for in claim 18.
Regarding claim 20, Lee in view of Chang teaches the device of claim 18.
Lee discloses wherein: the etching stop layer (600) has a step structure at an edge of the liner layer (500) (see Lee, FIG. 7).
Allowable Subject Matter
Claims 3, 9 and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 11 would be allowable if rewritten to overcome the objection(s), set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Claims 10 and 17 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art of records, individually or in combination, do not disclose nor teach “wherein: the via structure has an enlarged bottom critical dimension along the first direction” in combination with other limitations as recited in claim 3.
The prior art of record, Chang, teaches wherein: the etching stop layer is etched by a wet etching process using a chemical solution with a pH value in a range from 5 to 6.8. The prior art of records, individually or in combination, do not disclose nor teach “wherein: the liner layer is etched by a wet etching process using a chemical solution with a pH value in a range from 5 to 6.8” in combination with other limitations as recited in claim 9.
The prior art of record, Chang, teaches wherein: a sidewall of the hourglass-shaped profile has a first sidewall portion above the waist plane and a second sidewall portion below the waist plane, and the first sidewall portion forms a first angle with the top surface of the metal interconnect feature, and the second sidewall portion forms a second angle with the top surface of the metal interconnect feature. The prior art of records, individually or in combination, do not disclose nor teach “wherein the first angle is in a range from 95° to 140° and the second angle is in a range from 30° to less than 90°” in combination with other limitations as recited in claim 11.
The prior art of record, Lee, discloses wherein: the liner layer is a cobalt (Co) layer. The prior art of record, Chang, teaches wherein the etching stop layer to form the via structure is etched by a wet etching process using a chemical solution with a pH value in a range from 5 to 6.8. The prior art of records, individually or in combination, do not disclose nor teach “the cobalt layer to form the via structure is etched by a wet etching process using a chemical solution with a pH value in a range from 5 to 6.8.” in combination with other limitations as recited in claim 16.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHIH TSUN A CHOU whose telephone number is (408)918-7583. The examiner can normally be reached M-F 8:00-16:00 Arizona Time.
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/SHIH TSUN A CHOU/Primary Examiner, Art Unit 2811
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