DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over Claims 1-20 of U.S. Patent No. 10672820. Although the claims at issue are not identical, they are not patentably distinct from each other because
Regarding Claim 1, both the instant claim 1 and claims 1-20 of ‘820 recite, a method, comprising: forming a first interconnection structure on a first semiconductor substrate having first semiconductor devices formed therein, and the first interconnection structure comprising a first shunt trace; forming a first bonding layer on the first interconnection structure, the first bonding layer comprising a first dielectric layer and first conductors embedded in the first dielectric layer, and the first conductors being electrically connected to the first shunt trace; forming a second interconnection structure on a second semiconductor substrate having second semiconductor devices formed therein, and the second interconnection structure comprising a second shunt trace; forming a second bonding layer on the second interconnection structure, the second bonding layer comprising a second dielectric layer and second conductors embedded in the second dielectric layer, and the second conductors being electrically connected to the second shunt trace; and electrically connecting the first shunt trace and the second shunt trace through a bonding process of the first conductors and the second conductors.
Regarding Claim 2, both the instant claim 2 and claims 1-20 of ‘820 recite, wherein the bonding process of the first conductors and the second conductors comprises: bonding the first dielectric layer and the second dielectric layer; and bonding the first conductors and the second conductors.
Regarding Claim 3, both the instant claim 3 and claims 1-20 of ‘820 recite, wherein the bonding process of the first conductors and the second conductors comprises: performing a treatment for dielectric bonding between the first dielectric layer and the second dielectric layer; and performing a thermal annealing for conductor bonding between the first conductors and the second conductors.
Regarding Claim 4, both the instant claim 4 and claims 1-20 of ‘820 recite, wherein a process temperature of the thermal annealing for conductor bonding is higher than that of the treatment for dielectric bonding.
Regarding Claim 5, both the instant claim 5 and claims 1-20 of ‘820 recite, wherein the treatment for dielectric bonding between the first dielectric layer and the second dielectric layer is performed at temperature ranging from about 100 Celsius degree to about 150 Celsius degree, and the thermal annealing for conductor bonding is performed at temperature ranging from about 300 Celsius degree to about 400 Celsius degree.
Regarding Claim 6, both the instant claim 6 and claims 1-20 of ‘820 recite, wherein the conductor bonding between the first conductors and the second conductors comprises a via-to-via bonding, a pad-to-pad bonding or a via-to-pad bonding.
Regarding Claim 7, both the instant claim 7 and claims 1-20 of ‘820 recite,
performing a singulation process after electrically connecting the first shunt trace and the second shunt trace through the bonding process of the first conductors and the second conductors.
Regarding Claim 8, both the instant claim 8 and claims 1-20 of ‘820 recite, a method, comprising: forming a first interconnection structure on a first semiconductor substrate having first semiconductor devices formed therein, and the first interconnection structure comprising a first trace; forming a first dielectric layer and first conductors on the first interconnection structure, the first conductors being embedded in the first dielectric layer, and the first conductors being electrically connected to the first trace; forming a second interconnection structure on a second semiconductor substrate having second semiconductor devices formed therein, and the second interconnection structure comprising a second trace; forming on a second dielectric layer and second conductors on the second interconnection structure, the second conductors being embedded in the second dielectric layer, and the second conductors being electrically connected to the second trace; and electrically connecting the first shunt trace and the second shunt trace through a bonding process of the first conductors and the second conductors such that a shunt path provided by the first conductors and the second conductors is generated between the first trace and the second trace.
Regarding Claim 9, both the instant claim 9 and claims 1-20 of ‘820 recite,
wherein the bonding process of the first conductors and the second conductors comprises: performing a treatment for dielectric bonding between the first dielectric layer and the second dielectric layer; and performing a thermal annealing for conductor bonding between the first conductors and the second conductors.
Regarding Claim 10, both the instant claim 10 and claims 1-20 of ‘820 recite,
wherein a process temperature of the thermal annealing for conductor bonding is higher than that of the treatment for dielectric bonding.
Regarding Claim 11, both the instant claim 11 and claims 1-20 of ‘820 recite,
wherein the treatment for dielectric bonding between the first dielectric layer and the second dielectric layer is performed at temperature ranging from about 100 Celsius degree to about 150 Celsius degree, and the thermal annealing for conductor bonding is performed at temperature ranging from about 300 Celsius degree to about 400 Celsius degree.
Regarding Claim 12, both the instant claim 12 and claims 1-20 of ‘820 recite, wherein the conductor bonding between the first conductors and the second conductors comprises a via-to-via bonding, a pad-to-pad bonding or a via-to-pad bonding.
Regarding Claim 13, both the instant claim 13 and claims 1-20 of ‘820 recite, wherein the bonding process of the first conductors and the second conductors comprises dielectric-to-dielectric bonding and metal-to-metal bonding.
Regarding Claim 14, both the instant claim 14 and claims 1-20 of ‘820 recite, performing a singulation process after electrically connecting the first shunt trace and the second shunt trace through the bonding process of the first conductors and the second conductors.
Regarding Claim 15, both the instant claim 15 and claims 1-20 of ‘820 recite, a method, comprising: providing a first semiconductor wafer comprising photo-sensing chips arranged in array, the first semiconductor wafer comprising a first shunt trace and a first bonding layer, the first bonding layer comprising a first dielectric layer and at least one first conductor group penetrating through the first dielectric layer; providing a second semiconductor wafer comprising logic integrated circuit chips arranged in array, the second semiconductor wafer comprising a second shunt trace and a second bonding layer, the second bonding layer comprising a second dielectric layer and at least one second conductor group penetrating through the second dielectric layer; and bonding the first bonding layer to the second bonding layer, wherein a shunt path is formed by the first conductors and the second conductors disposed between the first shunt trace and the second shunt trace.
Regarding Claim 16, both the instant claim 16 and claims 1-20 of ‘820 recite, wherein the first bonding layer further comprises at least one first isolation portion penetrating through the first dielectric layer and electrically insulated from the first conductors, and at least one of the first conductors is surrounded by the at least one first isolation portion.
Regarding Claim 17, both the instant claim 17 and claims 1-20 of ‘820 recite, wherein the at least one first isolation portion is bonded to the second dielectric layer after bonding the first bonding layer to the second bonding layer.
Regarding Claim 18, both the instant claim 18 and claims 1-20 of ‘820 recite, wherein second bonding layer further comprises at least one second isolation portion penetrating through the second dielectric layer and electrically insulated from the second conductors, and at least one of the second conductors is surrounded by the at least one second isolation portion.
Regarding Claim 19, both the instant claim 19 and claims 1-20 of ‘820 recite, wherein the at least one first isolation portion and the at least one second isolation portion are electrically floated.
Regarding Claim 20, both the instant claim 20 and claims 1-20 of ‘820 recite, wherein the at least one first isolation portion is bonded to the at least one second isolation portion after bonding the first bonding layer to the second bonding layer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over Claims 1-20 of U.S. Patent No. 12021103. Although the claims at issue are not identical, they are not patentably distinct from each other because
Regarding Claim 1, both the instant claim 1 and claims 1-20 of ‘103 recite, a method, comprising: forming a first interconnection structure on a first semiconductor substrate having first semiconductor devices formed therein, and the first interconnection structure comprising a first shunt trace; forming a first bonding layer on the first interconnection structure, the first bonding layer comprising a first dielectric layer and first conductors embedded in the first dielectric layer, and the first conductors being electrically connected to the first shunt trace; forming a second interconnection structure on a second semiconductor substrate having second semiconductor devices formed therein, and the second interconnection structure comprising a second shunt trace; forming a second bonding layer on the second interconnection structure, the second bonding layer comprising a second dielectric layer and second conductors embedded in the second dielectric layer, and the second conductors being electrically connected to the second shunt trace; and electrically connecting the first shunt trace and the second shunt trace through a bonding process of the first conductors and the second conductors.
Regarding Claim 2, both the instant claim 2 and claims 1-20 of ‘103 recite, wherein the bonding process of the first conductors and the second conductors comprises: bonding the first dielectric layer and the second dielectric layer; and bonding the first conductors and the second conductors.
Regarding Claim 3, both the instant claim 3 and claims 1-20 of ‘103 recite, wherein the bonding process of the first conductors and the second conductors comprises: performing a treatment for dielectric bonding between the first dielectric layer and the second dielectric layer; and performing a thermal annealing for conductor bonding between the first conductors and the second conductors.
Regarding Claim 4, both the instant claim 4 and claims 1-20 of ‘103 recite, wherein a process temperature of the thermal annealing for conductor bonding is higher than that of the treatment for dielectric bonding.
Regarding Claim 5, both the instant claim 5 and claims 1-20 of ‘103 recite, wherein the treatment for dielectric bonding between the first dielectric layer and the second dielectric layer is performed at temperature ranging from about 100 Celsius degree to about 150 Celsius degree, and the thermal annealing for conductor bonding is performed at temperature ranging from about 300 Celsius degree to about 400 Celsius degree.
Regarding Claim 6, both the instant claim 6 and claims 1-20 of ‘103 recite, wherein the conductor bonding between the first conductors and the second conductors comprises a via-to-via bonding, a pad-to-pad bonding or a via-to-pad bonding.
Regarding Claim 7, both the instant claim 7 and claims 1-20 of ‘103 recite,
performing a singulation process after electrically connecting the first shunt trace and the second shunt trace through the bonding process of the first conductors and the second conductors.
Regarding Claim 8, both the instant claim 8 and claims 1-20 of ‘103 recite, a method, comprising: forming a first interconnection structure on a first semiconductor substrate having first semiconductor devices formed therein, and the first interconnection structure comprising a first trace; forming a first dielectric layer and first conductors on the first interconnection structure, the first conductors being embedded in the first dielectric layer, and the first conductors being electrically connected to the first trace; forming a second interconnection structure on a second semiconductor substrate having second semiconductor devices formed therein, and the second interconnection structure comprising a second trace; forming on a second dielectric layer and second conductors on the second interconnection structure, the second conductors being embedded in the second dielectric layer, and the second conductors being electrically connected to the second trace; and electrically connecting the first shunt trace and the second shunt trace through a bonding process of the first conductors and the second conductors such that a shunt path provided by the first conductors and the second conductors is generated between the first trace and the second trace.
Regarding Claim 9, both the instant claim 9 and claims 1-20 of ‘103 recite,
wherein the bonding process of the first conductors and the second conductors comprises: performing a treatment for dielectric bonding between the first dielectric layer and the second dielectric layer; and performing a thermal annealing for conductor bonding between the first conductors and the second conductors.
Regarding Claim 10, both the instant claim 10 and claims 1-20 of ‘103 recite,
wherein a process temperature of the thermal annealing for conductor bonding is higher than that of the treatment for dielectric bonding.
Regarding Claim 11, both the instant claim 11 and claims 1-20 of ‘103 recite,
wherein the treatment for dielectric bonding between the first dielectric layer and the second dielectric layer is performed at temperature ranging from about 100 Celsius degree to about 150 Celsius degree, and the thermal annealing for conductor bonding is performed at temperature ranging from about 300 Celsius degree to about 400 Celsius degree.
Regarding Claim 12, both the instant claim 12 and claims 1-20 of ‘103 recite, wherein the conductor bonding between the first conductors and the second conductors comprises a via-to-via bonding, a pad-to-pad bonding or a via-to-pad bonding.
Regarding Claim 13, both the instant claim 13 and claims 1-20 of ‘103 recite, wherein the bonding process of the first conductors and the second conductors comprises dielectric-to-dielectric bonding and metal-to-metal bonding.
Regarding Claim 14, both the instant claim 14 and claims 1-20 of ‘103 recite, performing a singulation process after electrically connecting the first shunt trace and the second shunt trace through the bonding process of the first conductors and the second conductors.
Regarding Claim 15, both the instant claim 15 and claims 1-20 of ‘103 recite, a method, comprising: providing a first semiconductor wafer comprising photo-sensing chips arranged in array, the first semiconductor wafer comprising a first shunt trace and a first bonding layer, the first bonding layer comprising a first dielectric layer and at least one first conductor group penetrating through the first dielectric layer; providing a second semiconductor wafer comprising logic integrated circuit chips arranged in array, the second semiconductor wafer comprising a second shunt trace and a second bonding layer, the second bonding layer comprising a second dielectric layer and at least one second conductor group penetrating through the second dielectric layer; and bonding the first bonding layer to the second bonding layer, wherein a shunt path is formed by the first conductors and the second conductors disposed between the first shunt trace and the second shunt trace.
Regarding Claim 16, both the instant claim 16 and claims 1-20 of ‘103 recite, wherein the first bonding layer further comprises at least one first isolation portion penetrating through the first dielectric layer and electrically insulated from the first conductors, and at least one of the first conductors is surrounded by the at least one first isolation portion.
Regarding Claim 17, both the instant claim 17 and claims 1-20 of ‘103 recite, wherein the at least one first isolation portion is bonded to the second dielectric layer after bonding the first bonding layer to the second bonding layer.
Regarding Claim 18, both the instant claim 18 and claims 1-20 of ‘103 recite, wherein second bonding layer further comprises at least one second isolation portion penetrating through the second dielectric layer and electrically insulated from the second conductors, and at least one of the second conductors is surrounded by the at least one second isolation portion.
Regarding Claim 19, both the instant claim 19 and claims 1-20 of ‘103 recite, wherein the at least one first isolation portion and the at least one second isolation portion are electrically floated.
Regarding Claim 20, both the instant claim 20 and claims 1-20 of ‘103 recite, wherein the at least one first isolation portion is bonded to the at least one second isolation portion after bonding the first bonding layer to the second bonding layer.
Examiner is including Sukekawa 9666573 as pertinent prior art that is not relied upon on this rejection but that discloses hybrid bonding interface.
Conclusion
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/FAZLI ERDEM/Primary Examiner, Art Unit 2812 5/30/2026
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