DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 12-20 rejected under 35 U.S.C. 103 as being unpatentable over Ping et al (U.S. Pub #2022/0068937), in view of Kim et al (U.S. Pub #2018/0040561).
With respect to claim 12, Ping teaches a method of forming a semiconductor structures, comprising:
forming a first dielectric layer (Fig. 4, 104) on a substrate;
depositing a sacrificial layer (Fig. 9, 119 and Paragraph 64) on the substrate;
forming a plurality of bit line structures (Fig. 12, 120 and Paragraph 70) in the sacrificial layer, wherein the first dielectric layer extends in a first direction, and the bit line structures extend in a second direction vertical to the first direction;
removing the sacrificial layer (Fig. 14 and Paragraph 80).
Ping does not teach
forming a plurality of word line structures in a substrate;
wherein the first dielectric layer vertical aligns with the word line structures,
forming a plurality of capacitor contacts on the substrate, wherein locations of capacitor contacts defined by the first dielectric layer and the bit line structures.
Kim teaches
forming a plurality of word line structures (Fig. 1B-1C, WL) in a substrate;
wherein a first dielectric layer (see Figs. 1C, D-D’ , the first dielectric layer 110 is vertically over WL) vertical aligns with the word line structures,
forming a plurality of capacitor contacts (Fig. 1B-1C, CPS and Paragraph 29. CPS makes contact with capacitor DSP, Paragraph 53) on the substrate,
wherein locations of capacitor contacts defined by the first dielectric layer and the bit line structures (see Fig. 1B A-A’, the location of CPS is between adjacent portions of 110 and BLS).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide word line structure and capacitor contacts in the structure of Ping as taught by Kim in order to make contact with a data storage part for the memory (Paragraph 53) and to provide word lines for addressing the data storage parts.
With respect to claim 13, Ping teaches forming a plurality of bit line contacts (Fig. 1, 101) is prior to the forming the sacrificial layer (Fig. 9, 119) on the substrate.
Kim teaches that bit line contacts (Fig. 1B-1C, BLS) are between the word line structures (Fig. 1B-1B, WL+105).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide word line structures in the structure of Ping such that the bit line contact are between the word line structures in order to achieve the predictable result of individually addressing the data storage parts.
With respect to claim 14, Ping teaches that the forming the plurality of bit line contacts between the word line structures comprising:
forming a second dielectric layer (Fig. 8, 118) on the first dielectric layer (Fig. 8, 104);
forming a plurality of bit line contact holes (Fig. 10) between the first dielectric layer and the second dielectric layer;
forming a conductive material (Fig. 11, 120) in the bit line contact holes; and
etching a top portion of the conductive material (Fig. 12, 120).
With respect to claim 15, Ping teaches that the second dielectric layer (Fig. 8-12, 118) defines a dimension of the bit line contacts (Fig. 12, 120).
With respect to claim 16, Kim teaches that side walls of the word line structures (Fig. 1C, WL+105) vertical aligns with side walls of the first dielectric layer (Fig. 1C, 110).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a word line that vertically aligns with the first dielectric layer of Ping as taught by Kim in order to achieve the predictable result of individually addressing the data storage parts.
With respect to claim 17, Kim teaches that forming a plurality of capacitor contact holes (Fig. 9B, 145) between the bit line structures; depositing a conductive layer (Fig. 9B, 151) in the capacitor contact holes; and etching a top portion of the conductive layer (Fig. 12B, 153).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the capacitor contacts as taught by Kim in order to achieve the predictable result of making contact with a data storage part for the memory (Paragraph 53)
With respect to claim 18, Ping and Kim does not teach that a bottom of the capacitor contact holes is lower than a top surface of the substrate about 40nm.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to the depth of the capacitor holes into the substrate to be about 40 nm because it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. (In re Aller, 105 USPQ 233). See also MPEP 2144.05 II.
With respect to claim 19, Ping does not teach the method further comprising: forming a first landing pad on the capacitor contacts; and
forming a second landing pad on the first landing pad, wherein the second landing pad overlies on a portion of a top surface of the bit line structures.
Kim teaches
forming a first landing pad (Fig. 1B, 157) on the capacitor contacts; and
forming a second landing pad (Fig. 1B, 159) on the first landing pad, wherein the second landing pad overlies on a portion of a top surface of the bit line structures (Fig. 1B, BLS).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a first landing pad and second landing pad in the structure of Ping as taught by Kim in order to achieve the predictable result of forming a surface for provide the data storage part (Fig. 1B, DSP).
With respect to claim 20, Kim teaches that the forming a first landing pad on the capacitor contacts comprising:
forming a conductive material (Fig. 1B, 157) on the capacitor contacts; and removing a top portion of the conductive material (Fig. 1B, portion of 157 is removed to form LPI structure), wherein a top surface of the first landing pad is coplanar with a top surface of the bit line structures (Fig. 1B, 157 and BLS are coplanar along the plane of portion LPI).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the capacitor contacts in the structure of Ping as taught by Kim in order to provide a landing pad surface for provide the data storage part.
Allowable Subject Matter
Claims 1-11 are allowed.
The following is an examiner’s statement of reasons for allowance: the best prior art of record does not teach or fairly suggest
in claim 1:
forming a hard mask layer on a substrate;
forming a plurality of word line trenches in the substrate and the hard mask layer;
forming a plurality of word line structures in the word line trenches, wherein a top surface of the word line structures is coplanar with a top surface of the substrate; forming a first dielectric layer in the word line trenches and extending upward from the substrate, wherein a top surface of the first dielectric layer is coplanar with a top surface of the hard mask layer;
removing the hard mask layer to define a plurality of trenches in the first dielectric layer;
forming a sacrificial layer in the trenches;.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENJAMIN P SANDVIK whose telephone number is (571)272-8446. The examiner can normally be reached M-F: 10-6.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at (571)-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/BENJAMIN P SANDVIK/Primary Examiner, Art Unit 2812
Prosecution Insights