DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (US 2013/0119449 A1).
Regarding claim 1, Chen teaches a varactor structure (Figs. 1-3 of Chen), comprising:
a substrate (61);
a first conductive layer (57 and 39) located on the substrate;
a second conductive layer (35 and 37) located on the first conductive layer;
a first dielectric layer (29 and 59 in Fig. 3) located between the substrate and the first conductive layer;
a second dielectric layer (25) located between the first conductive layer and the second conductive layer; and
a first doped region (left doped region 63) and a second doped region (right doped region 63) located in the substrate at two sides of the first conductive layer (as shown in Fig. 3), wherein the second conductive layer is electrically connected to the first doped region and the second doped region (as shown in Fig. 3).
Regarding claim 2, Chen teaches all limitations of the varactor structure of claim 1, and further comprising: a first conductive wire (43 and 47) electrically connected to the second conductive layer, the first doped region, and the second doped region (as shown in Fig. 3, the wires 43 and 47 are connected to wires 35, 37 and first/second doped regions 63).
Regarding claim 3, Chen teaches all limitations of the varactor structure of claim 2, and also teaches wherein a top-view pattern of the first conductive wire comprises a ring shape (Fig. 3 is a cross-section view of the seal ring 15, which is a ring shape as shown in Fig. 1 of Chen).
Regarding claim 4, Chen teaches all limitations of the varactor structure of claim 2, and further comprising:
a first conductive plug (plug 31 that connects 43 to 37 in Fig. 3) located between the first conductive wire and the second conductive layer and electrically connected to the first conductive wire and the second conductive layer (as shown in Fig. 3 of Chen);
a second conductive plug (plug 31 that connects 37 to the left doped region 63 in Fig. 3) located between the first conductive wire and the first doped region and electrically connected (the term “electrically connected” means there can be elements in between these two elements, as long as there is a current flow between them) to the first conductive wire and the first doped region; and
a third conductive plug (plug 31 that connects 35 to the right doped region 63 in Fig. 3) located between the first conductive wire and the second doped region and electrically connected to the first conductive wire and the second doped region.
Regarding claim 5, Chen teaches all limitations of the varactor structure of claim 4, and further comprising: a second conductive wire (51 in Fig. 3) electrically connected to the first conductive layer.
Regarding claim 6, Chen teaches all limitations of the varactor structure of claim 5, and further comprising: a fourth conductive plug (plug 31 that connects 43 and 51 as shown in Fig. 3 of Chen) located between the second conductive wire and the first conductive layer and electrically connected to the second conductive wire and the first conductive layer.
Regarding claim 7, Chen teaches all limitations of the varactor structure of claim 1, and also teaches wherein the first conductive layer and the second conductive layer are extended in a first direction (in-out direction of the page in Fig. 3 of Chen, which is left-right direction in Fig. 1 of Chen).
Regarding claim 8, Chen teaches all limitations of the varactor structure of claim 7, and also teaches wherein a length of the first conductive layer (length of longer portion 57/39 in left-right direction in Fig. 1 of Chen) in the first direction is greater than a length of the second conductive layer (width of shorter portion of 35/37 in Fig. 1 in left-right direction) in the first direction.
Regarding claim 9, Chen teaches all limitations of the varactor structure of claim 7, and also teaches wherein the first doped region and the second doped region are arranged in a second direction (as shown in Fig. 3, the second direction is left-right direction in the longer section), and the first direction is intersected with the second direction.
Regarding claim 10, Chen teaches all limitations of the varactor structure of claim 1, and also teaches wherein a material of the first conductive layer comprises doped polysilicon (57 is made of polysilicon, as stated in [0017] of Chen) or a metal.
Regarding claim 11, Chen teaches all limitations of the varactor structure of claim 1, and also teaches wherein a material of the second conductive layer comprises a metal (35 and 37 are in metallization layer), a metal compound, or a combination thereof.
Regarding claim 12, Chen teaches all limitations of the varactor structure of claim 1, and also teaches wherein a material of the first dielectric layer comprises silicon oxide (as described in [0017] of Chen), a high-k material, or a combination thereof.
Regarding claim 13, Chen teaches all limitations of the varactor structure of claim 1, and also teaches wherein a material of the second dielectric layer comprises a low-k material or a high-k material (the range of low-k or high-k dielectric covers all the dielectric materials).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 14-19 are rejected under 35 U.S.C. 103 as being unpatentable over Chen, as applied to claim 1 above, and further in view of Tsai et al. (US 2017/0149404 A1).
Regarding claim 14, Chen teaches all limitations of the varactor structure of claim 1, but does not explicitly teach the varactor structure further comprising: a spacer located on a sidewall of the first conductive layer.
Tsai teaches a varactor structure (Fig. 11A of Tsai) comprising: a gate dielectric layer (1112 in Fig. 11A) disposed on a well region (1104a); a gate conductor (1110 in Fig. 11A) disposed on the gate dielectric layer (1112); spacers located on sidewalls of the gate conductor.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed spacers on sidewalls of the first conductive layer, as disclosed by Tsai, in order to protect and to isolate the first conductive layer from other elements.
Regarding claim 15, Chen teaches all limitations of the varactor structure of claim 1, but does not teach the varactor structure further comprising: a well region located in the substrate, wherein the first doped region and the second doped region are located in the well region.
Tsai teaches a varactor structure (Fig. 11A of Tsai) comprising: a gate dielectric layer (1112 in Fig. 11A) disposed on a well region (1104a); source/drain regions (1116, 1118 in Fig. 11A) formed in the well region; a gate conductor (1110 in Fig. 11A) disposed on the gate dielectric layer (1112); spacers located on sidewalls of the gate conductor.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the well region underneath the gate structure of Chen, as disclosed by Tsai, in order to improve the performance of the device.
Regarding claim 16, Chen in view of Tsai teaches all limitations of the varactor structure of claim 15, and also teaches wherein the first doped region, the second doped region, and the well region have a same conductivity type (as disclosed in Fig. 11A of Tsai, the well region and the S/D regions have the same conductivity).
Regarding claim 17, Chen teaches all limitations of the varactor structure of claim 1, but does not explicitly teach that the varactor structure further comprising: an isolation structure located in the substrate and defining an active region in the substrate.
Tsai teaches a varactor structure (Fig. 11A of Tsai) comprising: a gate dielectric layer (1112 in Fig. 11A) disposed on a well region (1104a) which is surrounded by an isolation structure (1108 in Fig. 11A); source/drain regions (1116, 1118 in Fig. 11A) formed in the well region; a gate conductor (1110 in Fig. 11A) disposed on the gate dielectric layer (1112); spacers located on sidewalls of the gate conductor.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the isolation structure surrounding the well region of Chen, as disclosed by Tsai, in order to isolation each transistor to the neighboring elements.
Regarding claim 18, Chen in view of Tsai teaches all limitations of the varactor structure of claim 17, and also teaches wherein the first doped region and the second doped region are located in the active region (as combined in claim 17 above, and shown in Fig. 11A of Tsai).
Regarding claim 19, Chen in view of Tsai teaches all limitations of the varactor structure of claim 17, and also teaches wherein the isolation structure comprises a shallow trench isolation structure (as shown in Fig. 11A of Tsai).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Chen, as applied to claim 1 above, and further in view of Nakaiso et al. (EP 3128544 B1).
Regarding claim 20, Chen teaches all limitations of the varactor structure of claim 1, and also teaches further comprising: a third dielectric layer (69 in Fig. 3 of Chen) located between the second dielectric layer and the substrate; but does not teach a fourth dielectric layer located on the second dielectric layer.
Nakaiso teaches a varactor structure (Fig. 5B of Nakaiso) in which different metallization layers (42-45) are disposed within different dielectric layers (31-32).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the structure of Chen in a step-by-step, layer-by-layer manner, i.e. to have formed metallization layers with different dielectric layers, as disclosed by Nakaiso, in order to have better quality of the interconnect structure. This is also a typical method of forming the interconnect structure.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUAN A HOANG whose telephone number is (571)270-0406. The examiner can normally be reached Monday-Friday 8-9am, 10am-6pm EST.
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/Tuan A Hoang/ Primary Examiner, Art Unit 2898
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