Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 2, 4, 5, and 10 are rejected under 35 U.S.C. 103 as being unpatentable over LaRoche et al. (US 20190097001 A1) in view of Ho et al. (US 20210134964 A1).
Regarding claim 1, FIG. 2B of LaRoche et al. teaches a semiconductor device, comprising:
a substrate (32; FIG. 2B; paragraph 0040);
a gate electrode (14; FIG. 2B; paragraph 0040) disposed on the substrate;
an etch stop layer (42; FIG. 2B; paragraph 0045);
an interlayer dielectric (ILD) (49; FIG. 2B; paragraph 0041) covering the gate electrode and the etch stop layer;
a field plate holder (54; FIG. 2B; paragraph 0043) embedded within the ILD and spaced apart from the substrate by the etch stop layer; and
a field plate (23; FIG. 2B; paragraph 0041) supported by the field plate holder.
LaRoche et al. does not teach the etch stop layer conformally extending from an upper surface of the gate electrode to an upper surface of the substrate.
FIG. 1 of Ho et al. teaches a contact etch stop layer (124; FIG. 1; paragraph 0017) deposed over a gate electrode (108; FIG. 1; paragraph 0017) and a substrate (102; FIG. 1; paragraph 0017).
LaRoche et al. and Ho et al. are both analogous with the claimed invention in that they in are semiconductor devices with field plates and gate electrodes. Therefore, it would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to modify LaRoche et al. so the etch stop layer conformally extends from an upper surface of the gate electrode to an upper surface of the substrate. This a is a known aspect of etching the dielectric portions of these inventions (paragraph 0014).
Regarding claim 2, the combination of LaRoche et al. in view of Ho et al. teach the semiconductor device of claim 1. FIG. 2B of LaRoche et al. further teaches the device wherein an upper surface of the field plate holder (54; FIG. 2B; paragraph 0043) is substantially aligned with an upper surface of the ILD (49; FIG. 2B; paragraph 0041).
Regarding claim 4, the combination of LaRoche et al. in view of Ho et al. teach the semiconductor device of claim 1. FIG. 2B of LaRoche et al. further teaches the device wherein
Regarding claim 5, the combination of LaRoche et al. in view of Ho et al. teach the semiconductor device of claim 1. FIG. 2B of LaRoche et al. further teaches the device wherein the field plate (23; FIG. 2B; paragraph 0041) is spaced apart from the substrate by the field plate holder (54; FIG. 2B; paragraph 0043) and the etch stop layer (42; FIG. 2B; paragraph 0045).
Regarding claim 10, the combination of LaRoche et al. in view of Ho et al. teach the semiconductor device of claim 1. FIG. 2B of LaRoche et al. further teaches the device wherein the field plate holder (54; FIG. 2B; paragraph 0043) has a substantially U-shaped profile.
Regarding claim 19, FIG. 2B of LaRoche et al. teaches a method of manufacturing a semiconductor device, comprising:
providing a substrate (32; FIG. 2B; paragraph 0040)
forming a gate electrode (14; FIG. 2B; paragraph 0040) on the substrate;
forming an etch stop layer (42; FIG. 2B; paragraph 0045);
forming an interlayer dielectric (ILD) (49; FIG. 2B; paragraph 0041) to cover the etch stop layer;
patterning the ILD to form a first opening (54; FIG. 2B; paragraph 0043);
forming a field plate holder (54; FIG. 2B; paragraph 0043) within the first opening of the ILD; and
forming a field plate (23; FIG. 2B; paragraph 0041) on the field plate holder.
LaRoche et al. does not teach the etch stop layer covering the substrate and the gate electrode.
FIG. 1 of Ho et al. teaches a contact etch stop layer (124; FIG. 1; paragraph 0017) deposed over a gate electrode (108; FIG. 1; paragraph 0017) and a substrate (102; FIG. 1; paragraph 0017).
LaRoche et al. and Ho et al. are both analogous with the claimed invention in that they in are semiconductor devices with field plates and gate electrodes. Therefore, it would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to modify LaRoche et al. so the etch stop layer conformally extends from an upper surface of the gate electrode to an upper surface of the substrate. This a is a known aspect of etching the dielectric portions of these inventions (paragraph 0014).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over LaRoche et al. in view of Ho et al. and further in view of Sandow et al. (US 20210175329 A1).
Regarding claim 3, the combination of LaRoche et al. in view of Ho et al. teach the semiconductor device of claim 1. Neither LaRoche et al. nor Ho et al. teach the device wherein the field plate holder comprises a semiconductor-containing material, a nitride-containing material, and a combination thereof, but FIG. 2B LaRoche does teach that the field plate holder is an electrode (54; FIG. 2B; paragraph 0043).
Sandow et al. teaches that electrode materials include semiconductor materials (paragraph 0024).
LaRoche et al., Ho et al., and Sandow et al. are all analogous with the claimed invention in that they in are semiconductor devices with field plates and gate electrodes. Therefore, it would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to modify LaRoche et al. so the field plate holder comprises a semiconductor-containing material. This is the result of semiconductor materials being known to be used for electrodes (paragraph 0024)
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over LaRoche et al. in view of Ho et al. and further in view of Qiao et al. (US 11424331 B1).
Regarding claim 6, the combination of LaRoche et al. in view of Ho et al. teach the semiconductor device of claim 1. LaRoche et al. does not teach a source/drain feature disposed within the substrate and defining a drift region within the substrate, and the field plate holder is disposed over the drift region.
FIG. 4 of Qiao et al. teaches a source region (105; FIG. 4; column 3, line 62) and a drain region (106; FIG. 4; column 3, line 60), where the drain region helps define a drift region (102; FIG. 4; column 3, line 42) that defines an oxide layer (132; FIG. 4; column 3, line 51) that holds a drain field plate (115; FIG. 4; column 3, line 52).
LaRoche et al., Ho et al., and Qiao et al. are all analogous with the claimed invention in that they in are semiconductor devices with field plates and gate electrodes. Therefore, it would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to modify LaRoche et al. to have a source/drain feature disposed within the substrate and defining a drift region within the substrate, with the field plate holder disposed over the drift region. The drift region channels the electric field through the device (column 1, lines 53-55).
Claims 11-13 and 16-18 is rejected under 35 U.S.C. 103 as being unpatentable over LaRoche et al. in view of Qiao et al. (US 11424331 B1).
Regarding claim 11, FIG. 2B of LaRoche et al. teaches a semiconductor device, comprising:
a substrate (32; FIG. 2B; paragraph 0040);
a gate electrode (14; FIG. 2B; paragraph 0040) disposed on the substrate; an etch stop layer (42; FIG. 2B; paragraph 0045);
an interlayer dielectric (ILD) (49; FIG. 2B; paragraph 0041) covering the gate electrode and the substrate;
a field plate holder (54; FIG. 2B; paragraph 0043) penetrating the ILD and spaced apart from the substrate by the etch stop layer; and
a field plate (23; FIG. 2B; paragraph 0041) disposed on the field plate holder.
LaRoche et al. does not teach a source/drain (S/D) feature disposed within the substrate and defining a drift region within the substrate and the first field plate holder penetrating the ILD and disposed over the drift region.
FIG. 4 of Qiao et al. teaches a source region (105; FIG. 4; column 3, line 62) and a drain region (106; FIG. 4; column 3, line 60), where the drain region helps define a drift region (102; FIG. 4; column 3, line 42) that defines an oxide layer (132; FIG. 4; column 3, line 51) that holds a drain field plate (115; FIG. 4; column 3, line 52).
LaRoche et al. and Qiao et al. are both analogous with the claimed invention in that they in are semiconductor devices with field plates and gate electrodes. Therefore, it would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to modify LaRoche et al. to have a source/drain feature disposed within the substrate and defining a drift region within the substrate, with the field plate holder disposed over the drift region. The drift region channels the electric field through the device (column 1, lines 53-55).
Regarding claim 12, the combination of LaRoche et al. in view of Qiao et al. teach the semiconductor device of claim 11. FIG. 2B of LaRoche et al. further teaches the device wherein the first field plate (23; FIG. 2B; paragraph 0041) is spaced apart from the ILD (49; FIG. 2B; paragraph 0041) by the first field plate holder (54; FIG. 2B; paragraph 0043).
Regarding claim 13, the combination of LaRoche et al. in view of Qiao et al. teach the semiconductor device of claim 12. LaRoche et al. further teaches the device wherein the first field plate (23; FIG. 2B; paragraph 0041) is spaced apart from the substrate (32; FIG. 2B; paragraph 0040) by the first field plate holder (54; FIG. 2B; paragraph 0043).
Regarding claim 16, the combination of LaRoche et al. in view of Qiao et al. teach the semiconductor device of claim 11. LaRoche et al. does not teach the device wherein the first field plate holder is free from vertically overlapping the S/D feature.
FIG. 4 of Qiao et al. teaches the source region (105; FIG. 4; column 3, line 62) and the drain region (106; FIG. 4; column 3, line 60) not vertically overlapping the oxide layer (132; FIG. 4; column 3, line 51).
it would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to modify LaRoche et al. to have the first field plate holder being free from vertically overlapping the S/D feature. This is the result of the necessary placement of the source and drain regions (column 2, line 20-28).
Regarding claim 17, the combination of LaRoche et al. in view of Qiao et al. teach the semiconductor device of claim 11. FIG. 2B of LaRoche et al. further teaches the device further comprising: an etch stop layer (42; FIG. 2B; paragraph 0045) disposed between the first field plate holder (23; FIG. 2B; paragraph 0041) and the substrate (32; FIG. 2B; paragraph 0040).
Regarding claim 18, the combination of LaRoche et al. in view of Qiao et al. teach the semiconductor device of claim 11. FIG. 2B of LaRoche et al. further teaches the device wherein an upper surface of the first field plate holder (54; FIG. 2B; paragraph 0043) is substantially aligned with an upper surface of the ILD (49; FIG. 2B; paragraph 0041).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over LaRoche et al. in view of Qiao et al. and further in view of Ma (US 20230163210 A1).
Regarding claim 14, the combination of LaRoche et al. in view of Qiao et al. teach the semiconductor device of claim 11. LaRoche et al. further teaches the device further comprising:
a second field plate holder (54; FIG. 2B; paragraph 0043) embedded within the ILD (49; FIG. 2B; paragraph 0041); and
a second field plate (23; FIG. 2B; paragraph 0041) disposed within the second field plate holder, wherein a bottom of the first field plate (23; FIG. 2B; paragraph 0041) is at an elevation different from that of the second field plate with respect to an upper surface of the substrate.
LaRoche et al. does not teach the second field plate holder being disposed above the drift region.
FIG. 1 of Ma teaches multiple field plates (132; FIG. 1; paragraph 0023) anchored by electrically insulative material (140; FIG. 1; paragraph 0024) over the drift zone (108; FIG. 1; paragraph 0016).
LaRoche et al., Qiao et al., and Ma are all analogous with the claimed invention in that they in are semiconductor devices with field plates and gate electrodes. Therefore, it would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to modify LaRoche et al. to have the second field plate holder being disposed above the drift region. This is a known result from the placement of drift regions (paragraph 0016).
Allowable Subject Matter
Claims 7-9, 15, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 7, the combination of LaRoche et al. in view of Ho et al. teach the semiconductor device of claim 1. Neither LaRoche et al. nor Ho et al. teach the device wherein the field plate holder comprises a first dielectric material layer and a second dielectric material layer on the first dielectric material layer.
FIG. 1 of Then et al. (US 20200227545 A1) teaches a high k dielectrics (172; FIG. 1; paragraph 0027) surrounding a source field plate (118; FIG. 1; paragraph 0027)drain field plate (120; FIG. 1; paragraph 0027). Then et al. does not teach a second dielectric material layer on the first dielectric material layer.
None of the located prior art teaches this limitation. Therefore, it would be improper in hindsight to modify LaRoche et al. to have a second dielectric material layer on the first dielectric material layer.
Claims 8 and 9 are dependent on claim 7 and thus are allowed.
Regarding claim 15, the combination of LaRoche et al. in view of Qiao et al. and further in view of Ma teach the semiconductor device of claim 14. Neither LaRoche et al., Qiao et al., nor Ma teach the device wherein a material of the first field plate holder is different from that of the second field plate holder. None of the located prior art teaches this limitation. Therefore, it would be improper in hindsight to modify LaRoche et al. so a material of the first field plate holder is different from that of the second field plate holder.
Regarding claim 20, the combination of LaRoche et al. in view of Ho et al. teach the semiconductor device of claim 19. Neither LaRoche et al. nor Ho et al. teach the device wherein forming the field plate holder comprises: forming a dielectric material within the opening of the ILD; and removing a portion of the dielectric material to form the field plate holder.
FIG. 3G and FIG. 3H of Then et al. teach a source field plate trench (340; FIG. 3G; paragraph 0040) and a drain field plate trench (340; FIG. 3G; paragraph 0040) being layered with a gate dielectric material (366; FIG. 3H; paragraph 0043). Then et al. does not teach removing a portion of the dielectric material to form the field plate holder (as the plate holder equivalent has already been formed).
None of the located prior art teaches this limitation. Therefore, it would be improper in hindsight to modify LaRoche et al. to remove a portion of the dielectric material to form the field plate holder.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Jin et al. (US 20220262948 A1) concerns an LDMOS device with a field plate in a dielectric layer, an etch stop layer, and a gate electrode. Hutzler et al. (US 20160293714 A1) concerns a semiconductor device with a field plate and gate electrode.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB A VLCEK whose telephone number is (571)272-9665. The examiner can normally be reached Mon-Fri, 9:00 AM -5:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/J.A.V./ Examiner, Art Unit 2817
/RATISHA MEHTA/ Primary Examiner, Art Unit 2817
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