DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 1-6 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention I, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 08/03/2026.
Applicant’s election without traverse of Invention II, Claims 7-17 in the reply filed on 08/03/2026 is acknowledged.
Specification
Amendments to Specification in Applicant’s Argument of 08/03/2026 are acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 8 and 11-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 8 recites the limitation "first carrying blocks" in the second line of the claim. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination, Examiner’s interprets “first carrying blocks” as “first carrying regions”.
Claim 11 recites the limitation " the second surface of the power chip " in second line of the claim. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination, Examiner’s interprets “the second surface of the power chip” as “the second surface of the chip body”.
Claim 12 recites the limitation " the inner plate surface… of the first ceramic board " in the fourth and fifth lines of the claim. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination, Examiner’s interprets of “the inner plate surface… of the first ceramic board” as “an inner plate surface… of the first ceramic board”.
Claim 14 recites the limitation " the second surface" in the fifth line of the claim. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination, Examiner’s interprets “the second surface” as “the second surface of the chip body”.
Regarding Claim 13, the claim cites the limitation, “annular side edge of the first carrier” and ““annular side edge of the second carrier” in the first and second lines of the claim. Fig 1 of the instant application discloses an isometric view of the device showing square shapes of the first and second carriers. Merriam-Webster dictionary defines, “annular” as “of, relating to, or forming a ring”. It is therefore unclear how the square shapes of the square first and second carriers can have an annular side edge. For purposes of examination, Examiner’s interprets the limitation of “annular side edge” as “outer side edge”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7-11, 13-15 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Buehler et al. (US 2024/0107675 A1, hereinafter Buehler ‘675) in view of Kang et al. (KR 20170068271 A, hereinafter Kang ‘271) in view of the following arguments.
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With respect to Claim 7 Buehler ‘675 discloses a power chip package structure (Fig 12), comprising:
a first carrier (1210/1205L/1235/1240/1245, Fig 12, Para [0209], hereinafter FC), including a first ceramic board (1205L, Fig 12, Para [0209]) and a first inner metal layer (upper layer 1210/1235/1240/1245, Fig 12, Para [0209], hereinafter FIML) formed on an inner surface (top surface of FC as shown in annotated Fig 12 of Buehler ‘675) of the first ceramic board (1250L), wherein the first inner metal layer (FIML) comprises at least one first connection pad (first connection pads of FIML shown in annotated Fig 12 of Buehler ‘675, hereinafter FCP), and a plurality of first carrying regions (plurality of first carrying regions of FIML shown in annotated Fig 12 of Buehler ‘675, hereinafter FCRS) spaced apart from each other and located outside (FCRS spaced apart from each other and located outside FCP shown in annotated Fig. 12 of Buehler ‘675) of the at least one first connection pad (FCP);
a first supporting portion (first supporting portion shown by oval area in annotated Fig 12 of Buehler ‘675, Para [0209], hereinafter FSP), including a plurality of supporting parts (supporting parts shown in annotated Fig 12 of Buehler ‘675), which are respectively formed on (supporting parts on FCRS shown in annotated Fig 12 of Buehler ‘675) the first carrying regions (FCRS) of the first inner metal layer (FIML); and
a power chip (1215, Fig 12, Para [0209]), comprising:
a chip body (chip body of 1215 disclosed in Fig 12 of Buehler ‘675, hereinafter CB) having a first surface (bottom of CB) and an opposing second surface (top of CB), and the first surface (bottom of CB) of the chip body (CB) is disposed on (CB on FSP is shown in annotated Fig 12 of Buehler ‘675) the first supporting portion (FSP); and
at least one first bonding pad (1225 and 1230, Fig 12, Para [0209]) formed on (CB on first surface shown in annotated Fig 12 of Buehler ‘675) the first surface (bottom of CB) of the chip body (CB), so that the power chip (1215) is electrically coupled to (1230 electrically connected to 1205L disclosed in Para [0209]) the first carrier (FC).
But Buehler ‘675 fails to expressly disclose at least one first conductive paste disposed on the at least one first connection pad.
Nevertheless, in a related endeavor (Fig 1-5 of Kang ‘271, Para references in provided English translation), Kang ‘271 teaches at least one first conductive paste (50a, Fig 4 of Kang ‘271, Para [0060] discloses 50a as solder) disposed on (50a on connection pad of 25 disclosed in annotated Fig 4 of Kang ‘271) the at least one first connection pad (connection pad of 25 disclosed in annotated Fig 4 of Kang ‘271);
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Kang ‘271’s teaching of at least one first conductive paste disposed on the at least one first connection pad into Buehler ‘675’s device. Buehler ‘675 is open to the structural arrangement of the supporting parts of the carrying regions of the first inner metal layer and the use of conductive pastes as disclosed in Para [0210]. Kang ‘271 discloses a power chip package with carriers on the top and bottom of a power chip and provides a structural arrangement and electrical connection of the power chip in the package. The ordinary artisan would have been motivated to modify Buehler ‘675 in the manner set forth above and have a high expectation of success, at least, because Kang ‘271’s teaching of using a conductive paste is a well-known method for the well-known advantage of creating a conductive connection between a chip and an interconnect structure.
As incorporated, the teachings of Kang ‘271 of first conductive paste (50a) of Kang ‘271 would be disposed on the at least one first connection pad (FCP) of Buehler ‘675 and the first bonding pads (1225 and 1230) of Buehler ‘675 would be connected to the conductive paste (50a).
With respect to Claim 8 Buehler ‘675 as modified by Kang ‘271 discloses all limitations of the power chip package structure according to claim 7, and Buehler ‘675 as modified by Kang ‘271 further discloses wherein the at least one first connection pad (left FCP as shown in annotated Fig 12 of Buehler ‘675) is connected to (disclosed in annotated Fig 12 of Buehler ‘675) at least one of the plurality of first carrying blocks (Note Examiner’s interpretation of “first carrying blocks” as “first carrying regions”) (FCRS) to be electrically coupled to (1225 electrically connected to FCRS disclosed in Para [0209], “A polyimide or flex circuit, which may include a base polyimide material 1235 with an internal copper layer 1240 and a coverlet 1245, may provide an interconnect … to the gate 1225”) corresponding one of the plurality of supporting parts (left supporting part as shown in annotated Fig 12 of Buehler ‘675).
With respect to Claim 9 Buehler ‘675 as modified by Kang ‘271 discloses all limitations of the power chip package structure according to claim 8 and Buehler ‘675 discloses further comprising:
a second carrier (1210/1205U, Fig 12, Para [0209], hereinafter SC), including a second ceramic board (1205U, Fig 12, Para [0209]) and a second inner metal layer (lower layer 1210 on SC as shown in annotated Fig 12, Para [0209], hereinafter SIML) formed on an inner plate surface (bottom of 1205U as shown Fig 12) of the second ceramic board (1205U), wherein the second inner metal layer (SIML) comprises at least one second connection pad (second connection pad of SIML shown in annotated Fig 12 of Buehler ‘675, hereinafter SCP), and a second carrying region (second carrying regions of SIML shown in annotated Fig 12 of Buehler ‘675, hereinafter SCR) spaced apart from (SCR spaced apart from SCP shown in annotated Fig. 12 of Buehler ‘675) the at least one second connection pad (SCP);
a second supporting portion (second supporting portion shown in annotated Fig 12 of Buehler ‘675, hereinafter SSP) formed on the second carrying region (SCR) of the second inner metal layer (SIML)(arrangements of SSP on SCR disclosed in annotated Fig 12 of Buehler ‘675); and
wherein the power chip (1215) includes at least one second bonding pad (1220, Fig 12, Para [0209]) formed on the second surface (top of CB) of the chip body (CB), wherein the second supporting portion (SSP) is disposed on (1220 on top of CB disclosed in Fig 12) the second surface (top of CB) of the chip body (CB), so that the power chip (1215) is electrically coupled to (1220 electrically connected to 1205U is disclosed in Para [0209]) the second carrier (1205U).
and Kang ‘271 further teaches at least one second conductive paste (61a as disclosed in Fig 4 of Kang ‘271 (note that description cites second conductive paste as 60a and Fig 4 cites second conductive paste as 61a, Para [0060])) disposed on the at least one second connection pad (upper pad of 50, Fig 4 of Kang ‘271, Para [0060]).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Kang ‘271’s further teaching of at least one second conductive paste disposed on the at least one second connection pad into Buehler ‘675 as modified by Kang ‘271’s device. Buehler ‘675 is open to the use of conductive pastes as disclosed in Para [0210]. Kang ‘271 discloses a power chip package with carriers on the top and bottom of a power chip and provides a structural arrangement and electrical connection of the power chip in the package. Kang ‘271 also teaches a power chip package with carriers on the top and bottom of a power chip and provides additional details of a structural arrangement and electrical connection of the power chip in the package. The ordinary artisan would have been motivated to further modify Buehler ‘675 as modified by Kang ‘271 in the manner set forth above, at least, because Kang ‘271’s teaching of conductive paste for connecting a power chip to an interconnect is a well-known material to achieve the advantage of making an electrical connect between a device and a package interconnect.
As incorporated, the further teachings of Kang ‘271 of a second conductive paste (61a) would be disposed on the second connection pad (SCP) of Buehler ‘675 as modified by Kang ‘271 and the at least one second bonding pad (1220) of Buehler ‘675 as modified by Kang ‘271 is connected to the at least one second conductive paste (61a of Kang ‘271).
With respect to Claim 10 Buehler ‘675 as modified by Kang ‘271 discloses all limitations of the power chip package structure according to claim 9 and Buehler ‘675 discloses further comprising a plurality of pins (1260/1265, Fig 12, Para [0209]), which are spaced apart from each other (1260 and 1265 spaced apart from each other disclosed in Fig 12) and are arranged outside of (1260 and 1265 arranged outside of 1215 disclosed in Fig 12) the power chip (1215), wherein each of the plurality of pins (1260/1265) is electrically coupled to at least one of the first carrier (FC) and the second carrier (SC)(Para [0209] discloses 1260/1265 connected to 1225/1230 and 1220, therefore it is obvious they are electrically coupled to FC and SC as Para [0209] also discloses 1225/1230 and 1220 connected to FC and SC respectively).
With respect to Claim 11 Buehler ‘675 as modified by Kang ‘271 discloses all limitations of the power chip package structure according to claim 10, and Buehler ‘675 discloses further wherein a top edge (top edge of 1260 and top edge of 1265 as shown in annotated Fig 12 of Beuhler ‘675) of each of the plurality of pins (1260/1265) does not protrude from the second surface of the power chip (Note Examiner’s interpretation of “the second surface of the power chip” as “the second surface of the chip body”) (top of CB)(annotated Fig 12 of Beuhler ‘675 discloses the top edges of 1260 and 1265 do not protrude from top of CB).
With respect to Claim 13 Buehler ‘675 as modified by Kang ‘271 discloses all limitations of the power chip package structure according to claim 9, wherein an annular side edge (Note above Examiner’s interpretation of “annular side edge” as “outer side edge”) (outer side edge of FC as shown in annotated Fig 12 of Beuhler ‘675) of the first carrier (FC) is flush with an annular side edge (Note above Examiner’s interpretation of “annular side edge” as “outer side edge”) (outer side edge of SC as shown in annotated Fig 12 of Beuhler ‘675) of the second carrier (SC)(annotated Fig 12 of Beuhler ‘675 discloses outer edge of FC flush with outer edge of SC).
With respect to Claim 14 Buehler ‘675 as modified by Kang ‘271 discloses all limitations of the power chip package structure according to claim 8, and Buehler ‘675 further discloses wherein number of the at least one first connection pad (FCP), number of the at least one first conductive paste (50a of Kang ‘271 as incorporated in Buehler ‘675 as disclosed above), and number of the at least one first bonding pad (1225 and 1230) are two for each (annotated Fig 12 of Beuhler ‘675 discloses at least two FCP, 50a and first connection pad), each of the first connection pads (FCP) is electrically coupled to one of the supporting parts (FCP electrically coupled to supporting part disclosed in annotated Fig 12 of Beuhler ‘675 as they share a Cu layer), and the two first bonding pads (1225 and 1230) are respectively a source pad (Para [0209] discloses 1230 as a source pad) and a gate pad (Para [0209] discloses 1225 as a gate pad), wherein the power chip (1215) further includes a second bonding pad (1220, Fig 12, Para [0209]) formed on the second surface (Note above Examiner’s interpretation of “the second surface” as “the second surface of the chip body”) (top of CB) and the second bonding pad (1220) is a drain pad (Para [0209] discloses 1220 as a drain connection).
With respect to Claim 15 Buehler ‘675 as modified by Kang ‘271 discloses all limitations of the power chip package structure according to claim 14, and Buehler ‘675 further teaches wherein the power chip package structure (power chip package of Fig 12) comprises a positioning portion (positioning portion of 1270 as shown in annotated Fig 12 of Beuhler ‘675, hereinafter PP) formed on the plurality of the supporting parts (supporting parts disclosed in annotated Fig 12 of Buehler ‘675), so that the positioning portion (PP) and the supporting parts (supporting parts disclosed in annotated Fig 12 of Buehler ‘675) jointly define a positioning slot (region between PP as shown in annotated Fig 12 of Buehler ‘675), wherein a bottom of the power chip (bottom of 1215 as shown in Fig 12) is located within (bottom of 1215 located within region between PP shown in annotated Fig 12 of Buehler ‘675) the positioning slot (region between PP as shown in annotated Fig 12 of Buehler ‘675), and a top of the power chip (top of 1215 as shown in Fig 12) protrudes from (top of 1215 protruding from region between PP is shown in annotated Fig 12 of Buehler ‘675)) the positioning slot (region between PP as shown in annotated Fig 12 of Buehler ‘675).
With respect to Claim 17 Buehler ‘675 as modified by Kang ‘271 discloses all limitations of the power chip package structure according to claim 8, and Buehler ‘675 further discloses wherein the power chip package structure adopts a wire-less architecture (Fig 2 of Buehler ‘675 disclose the power chip package (shown in Fig 2 as 140 or 145, Para [0166]) as part of an inverter (110) and Fig 3 of Buehler ‘675, Para [0168 and 0180] discloses invertor (disclosed as 300 in Fig 3) as part of a wireless network).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Beuhler ‘675 in view of Kang ‘271 in further view of Yang et al. (US 2014/0138075 A1, hereinafter Yang ‘075), in view of the following arguments.
With respect to Claim 12 Buehler ‘675 as modified by Kang ‘271 discloses all limitations of the power chip package structure according to claim 9, and Buehler ‘675 further discloses wherein, and the first carrier (FC) includes a first outer metal layer (lowermost 1210, Fig 12, Para [0209], hereinafter FOML), the second carrier (SC) includes a second outer metal layer (uppermost 1210, Fig 12, Para [0209], hereinafter SOML), wherein the first inner metal layer (FIML) and the first outer metal layer (FOML) are respectively plated on (FIML and FOML “bonded” on 1205L disclosed in Para [0209]) the inner plate surface (Note above Examiner’s interpretation of “the inner plate surface… of the first ceramic board” as “an inner plate surface… of the first ceramic board”)(top of 1205L as shown in annotated Fig 12 of Beuhler 675) and an outer plate surface (bottom of 1205L as shown in annotated Fig 12 of Beuhler 675) of the first ceramic board (1205L), and the second inner metal layer (SIML) and the second outer metal layer (SOML) are respectively plated on (SIML and SOML “bonded” on 1205U disclosed in Para [0209]) the inner plate surface (bottom of 1205U as shown Fig 12) and an outer plate surface (top of 1205U as shown Fig 12) of the second ceramic board (1205U).
But Buehler ‘675 as modified by Kang ‘271 fails to expressly disclose the first carrier and the second carrier are each a direct plated copper (DPC) ceramic substrate.
Nevertheless in a related endeavor (Fig 1A of Yang ‘075), Yang ‘075 teaches a carrier (120, Fig 1A of Yang ‘075, Para [0024]) as a direct plated copper (DPC) ceramic substrate (disclosed in Para [0024] of Yang ‘075).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Yang ‘075’s teaching of a carrier as a direct plated copper (DPC) ceramic substrate into Buehler ‘675 as modified by Kang ‘271’s device. Buehler ‘675 as modified by Kang ‘271 is open to the formation of the upper and lower carriers as it lists direct bond copper (DBC) or active metal brazing (AMB) as two examples of ceramic substrates with metal layers on top and bottom. Yang ‘075 teaches that a direct plated copper (DPC) ceramic substrate can be used instead of a DBC ceramic substrate in a power module. The ordinary artisan would have been motivated to modify Buehler ‘675 as modified by Kang ‘271 in the manner set forth above, at least, because Yang ‘075 teaching of a DPC ceramic substrate is a well-known alternative technology to DCB to create a ceramic based substrate for achieving the well-known advantage of having a substrate that can effectively remove heat from a high-power device.
As incorporated, the teaching of Yang ‘075 of using a DCB carrier would be used as the first carrier (FC) and second carrier (SC) substrate of Buehler ‘675 as modified by Kang ‘271, such that (FIML and FOML would be “plated” on 1205L and SIML and SOML would be “plated on” 1205U) of Buehler ‘675 as modified by Kang ‘271.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Buehler ‘675 in view of Kang ‘271 in further view of Teshima et al. (US 6,693,350 B2, hereinafter Teshima ‘350) in view of the following arguments.
With respect to Claim 16 Buehler ‘675 as modified by Kang ‘271 discloses all limitations of the power chip package structure according to claim 15, and Buehler ‘675 further discloses wherein a material (material of FIML) of the first inner metal layer (FIML) and a material (material of FSP) of the first supporting portion (FSP) are conductive materials (Para [0209] of Beuhler ‘675 discloses material of FIML and FSP as copper), and a material of the positioning portion (PP) is an insulating material (Para [0209] discloses 1270 as a dielectric material),
But Beuhler ‘675 as modified by Kang ‘271 fails to explicitly disclose wherein the at least one first conductive paste is a silver paste.
Nevertheless, in a related endeavor (Fig 3 of Teshima ‘350), Teshima ‘350 teaches the use of a silver paste as an alternative to a solder (Fig 3, Col 12, Lines 53-56 of Teshima ‘350).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Teshima ‘350’s teaching of wherein the at least one first conductive paste is a silver paste into Beuhler ‘675 as modified by Kang ‘271’s device. The ordinary artisan would have been motivated to modify Buehler ‘675 as modified by Kang ‘271 in the manner set forth above and have a high expectation of success, at least, because Teshima ‘350’s teaching of using a silver conductive paste is a well-known method for the well-known advantage of creating a conductive connection between a chip and an interconnect structure.
As incorporated, the teaching of Teshima ‘350 of using a silver conductive paste would be used as the conductive paste (50a) of Buehler ‘675 as modified by Kang ‘271.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL A. BERRY whose telephone number is (703)756-5637. The examiner can normally be reached M-F 8-5 EST.
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/PAUL A BERRY/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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