DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 10, 17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Philipp et al. (US 2009/003032 ‒hereinafter Philipp).
Regarding claim 1, Philipp discloses a semiconductor structure, comprising:
a memory device (100; fig. 1, further detailed 200a; fig. 3A) comprising:
a first electrode layer (202; fig. 3A);
a second electrode (208; fig. 3A) layer disposed over the first electrode layer (202); and
a data storage structure (204a/206; fig. 3A) interposed between the first electrode layer (202) and the second electrode layer (208), the data storage structure comprising:
a first layer (204a; fig. 3A) and
a second layer (206; fig. 3A), wherein a thermal conductivity of the first layer is greater than a thermal conductivity of the second layer (“second phase change material 206 [i.e. second layer] has a lower thermal conductivity than phase change material storage location 204a [i.e. first layer]” para 0042).
Regarding claim 10, Philipp discloses the semiconductor structure, further comprising: an interconnect structure (a via coupled to contact 210; para 0040) disposed over a semiconductor substrate (i.e. a wafer; fig. 4-11), wherein the memory device is embedded in the interconnect structure (fig. 3A).
Regarding claim 17, Philipp discloses a method for forming a semiconductor structure, comprising:
forming (i.e. fabricating; para 0049) a memory device (100; fig. 1, further detailed as memory 200a; fig. 3A) in an interconnect structure (memory 200a located in a via, and with contact 210 functions as an interconnect structure; fig. 3A para 0040) over a substrate (a wafer; para 0050), wherein the memory device comprises:
a data storage structure (204a/206; fig. 3A) formed over a first electrode layer (202; fig. 3A) and below a second electrode layer (208; fig. 3A), wherein the data storage structure comprises:
a first layer (204a; fig. 3A) formed over the first electrode layer (202); and
a second layer (206; fig. 3A) formed over the first layer (204a) and below the second electrode layer (208), wherein a thermal conductivity of the first layer is different from a thermal conductivity of the second layer (“second phase change material 206 [i.e. second layer] has a lower thermal conductivity than phase change material storage location 204a [i.e. first layer]” para 0042).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Philipp et al. (US 2009/0003032 ‒hereinafter Philipp) in view of Nishihara et al. (US 2005/0202204 ‒hereinafter Nishihara).
Regarding claim 2, Philipp does not expressly disclose the semiconductor structure, wherein a melting point of the first layer is higher than a melting point of the second layer.
Nishihara discloses wherein a melting point of the first layer is higher than a melting point of the second layer (“a melting point Tm1 of the first recording layer 41 is 630 degrees Celsius…[which is higher than] a melting point Tm2 of the second recording layer 42 is 550 degrees Celsius” para 0406).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Philipp is modifiable as taught by Nishihara for the purpose of improving the overall device by securing the integrity of its recording medium (para 0028 of Nishihara).
Regarding claim 19, Philipp does not expressly disclose the method, wherein a melting point of the first layer is higher than that of the second layer.
Nishihara discloses wherein a melting point of the first layer is higher than a melting point of the second layer (“a melting point Tm1 of the first recording layer 41 is 630 degrees Celsius…[which is higher than] a melting point Tm2 of the second recording layer 42 is 550 degrees Celsius” para 0406).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Philipp is modifiable as taught by Nishihara for the purpose of improving the overall device by securing the integrity of its recording medium (para 0028 of Nishihara).
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Philipp et al. (US 2009/0003032 ‒hereinafter Philipp) in view of Doi et al. (US 2005/0018593 ‒hereinafter Doi).
Regarding claim 4, Philipp does not expressly disclose the semiconductor structure, wherein the first layer has a ratio of nitrogen to oxygen greater than 0.25.
Doi discloses a first layer has a ratio of nitrogen to oxygen greater than 0.25 (i.e. in a group composition including nitrogen and oxygen, oxygen is preferably 50% to 95%, which is 0.5 to 0.95 and greater than 0.25; para 0042).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Philipp is modifiable as taught by Doi for the purpose of improving the overall performance by achieving a device that can withstand repeated access without compromising on manufacturing costs (para 0034 of Doi).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Philipp et al. (US 2009/003032 ‒hereinafter Philipp) in view of Wang et al. (US 2023/0354620 ‒hereinafter Wang).
Regarding claim 5, Philipp does not expressly disclose the semiconductor structure, wherein the memory device further comprises: a capping layer interposed between the data storage structure and the second electrode layer.
Wang discloses a capping layer (660; fig. 6A) interposed between the data storage structure (620; fig. 6A) and the second electrode layer (630; fig. 6A).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Philipp is modifiable as taught by Wang for the purpose of improving the overall performance of the device by reducing sneak current and shorting of elements (para 0075 of Wang).
Claim(s) 7-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Philipp et al. (US 2009/003032 ‒hereinafter Philipp) in view of Happ et al. (US 2008/0019170 ‒hereinafter Happ).
Regarding claim 7, Philipp does not expressly disclose the semiconductor structure, wherein the data storage structure further comprises: a third layer interposed between the first layer and the first electrode layer, wherein the third layer has a different material than the first layer and has a thermal conductivity greater than the thermal conductivity of the second layer.
Happ discloses a third layer (210b; fig. 4A) interposed between the first layer (210c/210a; fig. 4A) and the first electrode layer (206/202; fig. 4A), wherein the third layer has a different material (i.e. a variety of different phase change materials; para 0072, 0100) than the first layer (210c/210a) and has a thermal conductivity greater than the thermal conductivity of the second layer (dielectric 222 varies thermal environment between layers 210a-210c, essentially varying conductivity of the layers; para 0100, 0089).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Philipp is modifiable as taught by Happ for the purpose of managing induced temperatures of the device to facilitate data accessing schemes (para 0075 of Happ).
Regarding claim 8, Philipp does not expressly disclose the semiconductor structure, wherein a thickness of the first layer is greater than a thickness of the third layer.
Happ discloses a thickness (i.e. width) of the first layer (210a; fig. 4A) is greater than a thickness of the third layer (210b; fig. 4A).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Philipp is modifiable as taught by Happ for the purpose of managing induced temperatures of the device to facilitate data accessing schemes (para 0075 of Happ).
Claim(s) 9, 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Philipp et al. (US 2009/003032 ‒hereinafter Philipp) in view of Happ et al. (US 2008/0019170 ‒hereinafter Happ), and further in view of Doi et al. (US 2005/0018593 ‒hereinafter Doi).
Regarding claim 9, Philipp, as modified, does not expressly disclose the semiconductor structure, wherein the first layer is a metal oxynitride layer having a first metal, and the third layer comprises the first metal.
Doi discloses wherein the first layer is a metal oxynitride layer having a first metal, and the third layer comprises the first metal (layer(s) in a group composition including nitrogen and oxygen; para 0042).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Philipp is modifiable as taught by Doi for the purpose of improving the overall performance by achieving a device that can withstand repeated access without compromising on manufacturing costs (para 0034 of Doi).
Regarding claim 18, Philipp does not expressly disclose the method, wherein forming the device comprises: depositing a metal oxynitride layer over the first electrode layer; and performing a plasma treatment on the layer to form the first layer of the data storage structure.
Happ discloses depositing a layer over the first electrode layer (202; fig. 6); and performing a plasma treatment on the metal oxynitride layer to form the first layer of the data storage structure (para 0115).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Philipp is modifiable as taught by Happ for the purpose of managing induced temperatures of the device to facilitate data accessing schemes (para 0075 of Happ).
Doi discloses a metal oxynitride layer (layer(s) in a group composition including nitrogen and oxygen; para 0042).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Philipp is modifiable as taught by Doi for the purpose of improving the overall performance by achieving a device that can withstand repeated access without compromising on manufacturing costs (para 0034 of Doi).
Claim(s) 11-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over (Nishihara et al. (US 2005/0074694 ‒hereinafter Nishihara) in view of Wang et al. (US 2023/0354620 ‒hereinafter Wang).
Regarding claim 11, Nishihara discloses a semiconductor structure, comprising:
a memory device (memory device 54 comprising memory cells 51, further detailed as storage elements 38; fig. 8-10) over a substrate (39; fig. 8), the memory device comprising:
a first electrode layer (40; fig. 8);
a data storage structure (44; fig. 8) overlying the first electrode layer (40) and having a variable resistance (the data storage structure having variable resistance due to phase changes of layers 41 and 42; para 0244), the data storage structure comprising:
a stack (i.e. in a vertical direction) of a first dielectric material (401; fig. 8) and a second dielectric material (402; fig. 8), wherein the first dielectric material has a melting point (dielectric 401 can be made of a same material as dielectric layer 106; para 0240, further including oxides of Sn and Ga compositions or ZrO2 and HfO2 compounds, which has a melting point greater than 1000 degrees Celsius; para 0101, 0251, 0265)
a melting point of the second dielectric material (dielectric 402 can be made of a same material as dielectric layer 106; para 0240, further including oxides of Sn and Ga compositions or ZrO2 and HfO2 compounds, which has a melting point greater than 1000 degrees Celsius; para 0101, 0251, 0265); and
Nishihara does not expressly disclose embedded in an interconnect structure; first dielectric material has a melting point different from a melting point of the second dielectric material; a capping layer between the data storage structure and the first electrode layer or a top electrode layer overlying the data storage structure.
Nishihara teaches first and second dielectric layers having different materials or compositions (para 0276); further, melting points of dielectric material including oxides of Sn and Ga that constitute group GM are more than or equal to 1000 degrees Celsius (para 0251), or including ZrO2 and HfO2 compounds having a melting point at approximately 2700-2800 degrees Celsius (para 0095). Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Nishihara is modifiable as taught to have a first dielectric material (i.e. dielectric layer 401 including oxides of Sn and Ga with melting point of more than or equal to 1000 degrees Celsius) is different from a melting point of the second dielectric material (i.e. dielectric layer 402 including ZrO2 and HfO2 with melting point at approximately 2700-2800 degrees Celsius). Such modification is reasonably expected since one of ordinary skill in the art would be motivated to improve the device of Nishihara to secure the integrity of its recording medium (para 0028).
Wang discloses embedded in an interconnect structure (fig. 1B); a capping layer (660; fig. 6A) between the data storage structure (640/620; fig. 6A) and the first electrode layer (610; fig. 6A) or a top electrode layer (660) overlying the data storage structure (640/620).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Nishihara is modifiable as taught by Wang for the purpose of improving the overall performance of the device by reducing sneak current and shorting of elements (para 0075 of Wang).
Regarding claim 12, Nishihara does not expressly disclose the semiconductor structure, wherein the melting point of the first dielectric material is at least about 1.2 times greater than the melting point of the second dielectric material.
Nishihara teaches first and second dielectric layers having different materials or compositions (para 0276); further, melting points of dielectric material including oxides of Sn and Ga that constitute group GM are more than or equal to 1000 degrees Celsius (para 0251), or including ZrO2 and HfO2 compounds having a melting point at approximately 2700-2800 degrees Celsius (para 0095). Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Nishihara is modifiable as taught to have a first dielectric material (i.e. dielectric layer 402 including ZrO2 and HfO2 with melting point at approximately 2700-2800 degrees Celsius) is at least about 1.2 times greater than the melting point of the second dielectric material (i.e. dielectric layer 401 including oxides of Sn and Ga with melting point of more than or equal to 1000 degrees Celsius). Such modification is reasonably expected, where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art, and “about” is interpreted broadly. It has been held that without a particular unobvious purpose, produce an unexpected result, or a critical reason why the invention requires the particular limitation, the about range as disclosed by Nishihara makes the limitation obvious for purposes to improve the device by securing the integrity of its recording medium (para 0028).
Regarding claim 13, Nishihara does not expressly disclose the semiconductor structure, wherein a thermal conductivity of the first dielectric material is at least about 30 times greater than a thermal conductivity of the second dielectric material.
Nishihara teaches first and second dielectric layers having different materials or compositions (para 0276); further, thermal conductivity of dielectric material including SnO2SiC having a low thermal conductivity (para 0101), or including mixed plural oxides or carbides the thermal conductivity of the dielectric is varied (para 0254, 0265, 0453). Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Nishihara is modifiable as taught to have a first dielectric material is at least about 30 times greater than a thermal conductivity of the second dielectric material. Such modification is reasonably expected, where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art, and “at least about” is interpreted broadly. It has been held that without a particular unobvious purpose, produce an unexpected result, or a critical reason why the invention requires the particular limitation, the about range as disclosed by Nishihara makes the limitation obvious for purposes to improve the device by securing the integrity of its recording medium (para 0028).
Claim(s) 14, 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over (Nishihara et al. (US 2005/0074694 ‒hereinafter Nishihara) in view of Wang et al. (US 2023/0354620 ‒hereinafter Wang), and further in view of Doi et al. (US 2005/0018593 ‒hereinafter Doi).
Regarding claim 14, Nishihara, as modified, does not expressly disclose the semiconductor structure, wherein the first dielectric material is a metal oxynitride layer.
Doi discloses wherein the first layer is a metal oxynitride layer (layer(s) in a group composition including nitrogen and oxygen; para 0042).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Nishihara is further modifiable as taught by Doi for the purpose of improving the overall performance by achieving a device that can withstand repeated access without compromising on manufacturing costs (para 0034 of Doi).
Regarding claim 15, Nishihara, as modified, does not expressly disclose the semiconductor structure, wherein a ratio of nitrogen to oxygen of the first dielectric material is less than 3.
Doi discloses a first layer has a ratio of nitrogen to oxygen is less than 3 (i.e. in a group composition including nitrogen and oxygen, oxygen is preferably 50% to 95%, which is 0.5 to 0.95 and less than 3; para 0042).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Philipp is modifiable as taught by Doi for the purpose of improving the overall performance by achieving a device that can withstand repeated access without compromising on manufacturing costs (para 0034 of Doi).
Allowable Subject Matter
Claim(s) 3, 6, 16, 20 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record and considered pertinent to the applicant's disclosure does not teach or suggest the claimed invention having the following limitation, in combination with the remaining claimed limitations.
With respect to dependent claim 3, the prior art fails to teach or suggest the claimed limitations, namely wherein the first layer is close to the first electrode layer, the second layer connected to the first layer is close to the second electrode layer, and a relative density of the first layer is less than a relative density of the second layer.
With respect to dependent claim 6, the prior art fails to teach or suggest the claimed limitations, namely sidewall spacers disposed on the second layer of the data storage structure and extending along sidewalls of the capping layer and the second electrode layer.
With respect to dependent claim 16, the prior art fails to teach or suggest the claimed limitations, namely third dielectric material interposed between the first dielectric material and the first electrode layer, and a melting point of the third dielectric material is higher than the melting point of the second dielectric material.
With respect to dependent claim 20, the prior art fails to teach or suggest the claimed limitations, namely a third layer on the first electrode layer; forming the first layer and the second layer on the third layer, wherein the first layer is interposed between the third layer and the second layer, and a thermal conductivity of the third layer is greater than the thermal conductivity of the second layer.
The allowable claims are supported in at least fig. 9 of the instant application.
Conclusion
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/UYEN SMET/
[AltContent: connector] Primary Examiner, Art Unit 2824
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