Prosecution Insights
Last updated: July 17, 2026
Application No. 18/675,186

LAYOUT OF STATIC RANDOM ACCESS MEMORY

Non-Final OA §102
Filed
May 28, 2024
Priority
Apr 12, 2024 — TW 113113756
Examiner
TRAPANESE, WILLIAM C
Art Unit
Tech Center
Assignee
United Microelectronics Corp.
OA Round
1 (Non-Final)
77%
Grant Probability
Favorable
1-2
OA Rounds
1y 0m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allowance Rate
493 granted / 640 resolved
+17.0% vs TC avg
Strong +21% interview lift
Without
With
+20.9%
Interview Lift
resolved cases with interview
Typical timeline
3y 2m
Avg Prosecution
25 currently pending
Career history
667
Total Applications
across all art units

Statute-Specific Performance

§101
1.4%
-38.6% vs TC avg
§103
78.2%
+38.2% vs TC avg
§102
15.2%
-24.8% vs TC avg
§112
0.4%
-39.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 640 resolved cases

Office Action

§102
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1-14 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Liao et al. (hereinafter Liao, US 2024/0120273). In regards to independent claim 1, Liao teaches a layout of a static random access memory (SRAM) device (Liao, Fig. 1, [0016]), comprising: a gate structure extending along a first direction on a substrate (Fig. 18A, 360); a source/drain region extending along a second direction adjacent to a first side and a second side of the gate structure (Fig. 18A, 116); a body region adjacent to a third side of the gate structure (Fig. 18A, white portion between 116); and a notch between the gate structure and the body region (The L formed by 360 cause a 90degree notch over the white body portion, Fig. 18A). In regards to dependent claim 2, Liao teaches wherein the notch exposes the body region (The L formed by 360 cause a 90degree notch over the white body portion, Fig. 18A). In regards to dependent claim 3, Liao teaches wherein the source/drain region and the body region comprise different conductive type ([0080]). In regards to dependent claim 4, Liao teaches the layout of a SRAM device of claim 2, wherein gate structure comprises a T-shape (Fig. 22 360). In regards to dependent claim 5, Liao teaches the layout of a SRAM device of claim 4, wherein the T-shape comprises: a horizontal portion extending along the direction; and a vertical portion extending along the second direction (Fig. 22 360). In regards to dependent claim 6, Liao teaches the layout of a SRAM device of claim 1, wherein the vertical portion comprises the notch (Fig. 22 360 90 degree angle). In regards to dependent claim 7, Liao teaches wherein the gate structure comprises a L-shape (Fig. 18A, 360). In regards to dependent claim 8, Liao teaches a first contact plug on the gate structure (360); a second contact plug and a third contact plug on the source/drain region (124); and a fourth contact plug on the body region (124). In regards to independent claim 9, Liao teaches a layout of a static random access memory (SRAM) device, comprising: a first pull-up (PU) transistor (Fig. 1); a second pull-up (PU) transistor (Fig. 1); a first pull-down (PD) transistor; (Fig. 1); a second pull-down (PD) transistor (Fig. 1);; a first pass gate (PG) transistor (Fig. 1);; a second pass gate (PG) transistor (Fig. 1);; a body region between the first PG transistor and the second PG transistor (Fig. 18A, white portion between 116); and a first notch between the first PG transistor and the body region (The L formed by 360 cause a 90degree notch over the white body portion, Fig. 18A). In regards to dependent claim 10, Liao teaches wherein the first notch exposes the body region (The L formed by 360 cause a 90degree notch over the white body portion, Fig. 18A). In regards to dependent claim 11, Liao teaches further comprising a second notch between the second PG transistor and the body region (The L formed by 360 cause a 90degree notch over the white body portion, Fig. 18A). In regards to dependent claim 12, Liao teaches wherein the second notch exposes the body region (The L formed by 360 cause a 90degree notch over the white body portion, Fig. 18A). In regards to independent claim 13, Liao teaches wherein a source/drain region of the first PG transistor and the body region comprise different conductive type ([0080]). In regards to independent claim 14, Liao teaches further comprising: a first contact plug on a first gate structure of the first PG transistor (360); a second contact plug on a second gate structure of the second PG transistor (124); and a metal interconnection connecting the first contact plug and the second contact plug (360). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM C TRAPANESE whose telephone number is (571)270-3304. The examiner can normally be reached Monday - Friday 7am-12pm & 8pm-10pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at (571)272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /WILLIAM C TRAPANESE/Primary Examiner, Art Unit 2812
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Prosecution Timeline

May 28, 2024
Application Filed
Jun 17, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
77%
Grant Probability
98%
With Interview (+20.9%)
3y 2m (~1y 0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 640 resolved cases by this examiner. Grant probability derived from career allowance rate.

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