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The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
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Information Disclosure Statement
The information disclosure statements (IDS) submitted on May 28, 2024, July 28, 2025 and April 8, 2026 were in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
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1. Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-26 of Patent No.: US 11,502,110 B2. in view of Jung et al. (Pub. No.: US 2011/0127518 A1).
Regarding Claim 1, Patent No.: US 11,502,110 B2 discloses
a display device, comprising: a base substrate (Claim 1); a lower interlayer insulating layer disposed on the base substrate (Claim 11); a first lower gate electrode disposed between the base substrate and the lower interlayer insulating layer (Claim 11); an oxide semiconductor layer disposed on the lower interlayer insulating layer (Claim 11); a first gate insulating layer disposed the oxide semiconductor layer (Claim 1); a first upper gate electrode disposed on the first gate insulating layer (Claim 1); and an upper interlayer insulating layer disposed on the first upper gate electrode, wherein the first upper gate electrode is interposed between the oxide semiconductor layer and the upper interlayer insulating layer (Claim 1), a capacitor electrode disposed on the same layer as the first lower gate electrode and spaced apart from the first lower gate electrode (Claim 13); an upper gate insulating layer disposed between the capacitor electrode and the base substrate (Claim 13); and a second gate electrode disposed between the upper gate insulating layer and the base substrate, wherein the second gate electrode overlaps the capacitor electrode (Claim 13), wherein: the lower interlayer insulating layer includes a first lower interlayer insulating layer and a second lower interlayer insulating layer (Claim 12), the first lower interlayer insulating layer is disposed between the first lower gate electrode and the second lower interlayer insulating layer, and the second lower interlayer insulating layer is disposed between the first lower interlayer insulating layer and the oxide semiconductor layer (Claim 12), the upper interlayer insulating layer includes a first upper interlayer insulating layer, a second upper interlayer insulating layer, and a third upper interlayer insulating layer (Claim 1), each of the second upper interlayer insulating layer and the third upper interlayer insulating layer includes silicon nitride (Claim 1), and a hydrogen concentration in the second upper interlayer insulating layer is less than a hydrogen concentration in the third upper interlayer insulating layer (Claim 1). Patent No.: US 11,502,110 B2 does not explicitly disclose a hydrogen concentration in the first upper interlayer insulating layer is less than the hydrogen concentration in the second upper interlayer insulating layer.
However, Jung et al., at least implicitly, discloses
a hydrogen concentration in the first upper interlayer insulating layer is less than the hydrogen concentration in the second upper interlayer insulating layer (Par. 0053-0065 – this prior art teaches that silicon oxide, the material for the first upper insulating layer, is deposited using a “mixing gas including SiH4 and N2O, … SiH4 is a source gas of Si, and N2O is a source gas of O”; now the silicon nitride or the silicon oxynitride, the material for the second or third upper insulating layer, is deposited using a “SiH4, N2O, and NH3,
SiH4, N2O, and NH3 are source gases of Si, O, and N, respectively”; in other words, first upper insulating layer is formed without using NH3 gas, whereas the second and third upper interlayer insulating layers are formed using NH3 gas as one of the reactant gas; it is implied in this prior art and also is well-known that NH3 gas is the prominent source of hydrogen incorporation in the growing layer; because the first upper interlayer insulating layer is deposited without NH3 gas, it will have lower hydrogen concentration than the second or third upper interlayer insulating layers which are deposited using NH3 gas) It would have been obvious to one having ordinary skill in the art at the time the invention was filed to use the teachings of Jung et al. to adapt a display device, comprising: a hydrogen concentration in the first upper interlayer insulating layer of Patent No.: US 11,502,110 B2 is less than the hydrogen concentration in the second upper interlayer insulating layer in order to make sure that the channel layer is not deteriorated by the influx of hydrogen from the porous silicon oxide layer.
Regarding Claim 2, modified Patent No.: US 11,502,110 B2, as applied to claim 1, discloses
the display device, wherein the hydrogen concentration in the first upper interlayer insulating layer is less than the hydrogen concentration in the third upper interlayer insulating layer (please see the rejection of claim 1).
Regarding Claim 3, modified Patent No.: US 11,502,110 B2, as applied to claim 1, discloses
the display device, wherein the first upper interlayer insulating layer has a thickness from 500 Å to 3000 Å (Claim 7)
Regarding Claim 4, modified Patent No.: US 11,502,110 B2, as applied to claim 1, discloses
the display device, further comprising: wherein the first lower interlayer insulating layer contacts the first lower gate electrode, and the first lower gate electrode overlaps the first upper gate electrode (Claim 12)
.
Regarding Claim 5, modified Patent No.: US 11,502,110 B2, as applied to claim 1, discloses
the display device, wherein: the oxide semiconductor layer includes a first channel region, a first drain region located at one side of the first channel region, and a first source region located at the other side of the first channel region (Claim 20); the first gate insulating layer is disposed on the first channel region of the oxide semiconductor layer and overlaps the first channel region of the oxide semiconductor layer and exposes upper surfaces of the first drain region and first source region of the oxide semiconductor layer (Claim 20); and the upper interlayer insulating layer covers the first upper gate electrode, the first gate insulating layer, and an upper surface of the oxide semiconductor layer exposed by the first source region and the first drain region (Claim 20).
Regarding Claim 6, modified Patent No.: US 11,502,110 B2, as applied to claim 5, discloses
the display device, wherein the first upper interlayer insulating layer directly contacts the first upper gate electrode, the first gate insulating layer, and the upper surface of the oxide semiconductor layer (Claim 20 together with claim 2).
Regarding Claim 7, modified Patent No.: US 11,502,110 B2, as applied to claim 1, discloses
the display device, wherein the second upper interlayer insulating layer is disposed between the first upper interlayer insulating layer and the third upper interlayer insulating layer (Claim 3 & claim 20).
Regarding Claim 8, modified Patent No.: US 11,502,110 B2, as applied to claim 7, discloses
the display device, wherein: the second upper interlayer insulating layer is disposed directly on the first upper interlayer insulating layer, and the third upper interlayer insulating layer is disposed directly on the second upper interlayer insulating layer (Claim 3 & claim 20).
Regarding Claim 9, modified Patent No.: US 11,502,110 B2, as applied to claim 1, discloses
the display device, wherein the hydrogen concentration in the second upper interlayer insulating layer is 1E+22 atoms/cm3 or less (Claim 5). .
Regarding Claim 10, modified Patent No.: US 11,502,110 B2, as applied to claim 1, discloses
the display device, further comprising: a first source electrode or a first drain electrode disposed on the upper interlayer insulating layer (Claim 9), wherein the first source electrode is connected to the oxide semiconductor layer through a first contact hole that penetrates the upper interlayer insulating layer (Claim 9), or the first drain electrode is connected to the oxide semiconductor layer through a second contact hole that penetrates the upper interlayer insulating layer (Claim 9).
Regarding Claim 11, modified Patent No.: US 11,502,110 B2, as applied to claim 10, discloses
the display device, further comprising: a first connection electrode disposed on the upper interlayer insulating layer (Claim 10), wherein the first connection electrode is disposed on the same layer as the first source electrode (Claim 10), and the first connection electrode is connected to the first upper gate electrode through a third contact hole that penetrates the upper interlayer insulating layer (Claim 10).
Regarding Claim 12, modified Patent No.: US 11,502,110 B2, as applied to claim 10, discloses
the display device, wherein the first lower gate electrode overlaps the first upper gate electrode (Claim 11).
Regarding Claim 13, modified Patent No.: US 11,502,110 B2, as applied to claim 12, discloses
the display device, wherein the first lower interlayer insulating layer includes silicon nitride, and the second lower interlayer insulating layer contains silicon oxide (Claim 12).
Regarding Claim 14, modified Patent No.: US 11,502,110 B2, as applied to claim 1, discloses
the display device, further comprising: a lower gate insulating layer disposed between the second gate electrode and the base substrate (Claim 14); and a polycrystalline silicon semiconductor layer disposed between the lower gate insulating layer and the base substrate (Claim 14), wherein the polycrystalline silicon semiconductor layer includes a second channel region that overlaps the second gate electrode (Claim 14).
Regarding Claim 15, modified Patent No.: US 11,502,110 B2, as applied to claim 14, discloses
the display device, further comprising: a second source electrode or a second drain electrode disposed on the same layer as the first source electrode (Claim 15), wherein the second source electrode is connected to the polycrystalline silicon semiconductor layer through a fourth contact hole that penetrates the upper interlayer insulating layer, the lower interlayer insulating layer, the upper gate insulating layer, and the lower gate insulating layer (Claim 15), or the second drain electrode is connected to the polycrystalline silicon semiconductor layer through a fifth contact hole that penetrates the upper interlayer insulating layer, the lower interlayer insulating layer, the upper gate insulating layer, and the lower gate insulating layer (Claim 15).
Regarding Claim 16, modified Patent No.: US 11,502,110 B2, as applied to claim 15, discloses
the display device, wherein the polycrystalline silicon semiconductor layer, the second gate electrode, the capacitor electrode, and at least one of the second source electrode and the second drain electrode constitute a driving transistor (Claim 16).
Regarding Claim 17, modified Patent No.: US 11,502,110 B2, as applied to claim 1, discloses
the display device, wherein the lower interlayer insulating layer further includes a third lower interlayer insulating layer disposed between the first lower interlayer insulating layer and the first lower gate electrode, the third lower interlayer insulating layer includes silicon nitride, and a hydrogen concentration in the third lower interlayer insulating layer is less than a hydrogen concentration in the first lower interlayer insulating layer (Claim 17).
Regarding Claim 18, modified Patent No.: US 11,502,110 B2, as applied to claim 1, discloses
the display device, wherein the lower interlayer insulating layer further includes a third lower interlayer insulating layer disposed between the first lower interlayer insulating layer and the second lower interlayer insulating layer, the third lower interlayer insulating layer includes silicon nitride, and a hydrogen concentration in the third lower interlayer insulating layer is less than a hydrogen concentration in the first lower interlayer insulating layer (Claim 18).
Regarding Claim 19, modified Patent No.: US 11,502,110 B2, as applied to claim 1, discloses
the display device, wherein the upper interlayer insulating layer further includes a fourth upper interlayer insulating layer disposed between the second upper interlayer insulating layer and the third upper interlayer insulating layer, the fourth upper interlayer insulating layer includes silicon nitride, and a hydrogen concentration in the fourth upper interlayer insulating layer is between the hydrogen concentration in the second upper interlayer insulating layer and the hydrogen concentration in the third upper interlayer insulating layer (Claim 8).
Regarding Claim 20, modified Patent No.: US 11,502,110 B2, as applied to claim 9, discloses
the display device, wherein the upper interlayer insulating layer further includes a fourth upper interlayer insulating layer disposed between the third upper interlayer insulating layer and the first source electrode, and a hydrogen concentration in the fourth upper interlayer insulating layer is less than the hydrogen concentration in the third upper interlayer insulating layer (Claim 19).
2. Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-19 of Patent No.: US 12,027,527 B2. in view of Jung et al. (Pub. No.: US 2011/0127518 A1).
Regarding Claim 1, Patent No.: US 12,027,527 B2 discloses
a display device, comprising: a base substrate (Claim 1); a lower interlayer insulating layer disposed on the base substrate (Claim 1); a first lower gate electrode disposed between the base substrate and the lower interlayer insulating layer (Claim 1); an oxide semiconductor layer disposed on the lower interlayer insulating layer (Claim 1); a first gate insulating layer disposed the oxide semiconductor layer (Claim 1); a first upper gate electrode disposed on the first gate insulating layer (Claim 1); and an upper interlayer insulating layer disposed on the first upper gate electrode, wherein the first upper gate electrode is interposed between the oxide semiconductor layer and the upper interlayer insulating layer (Claim 1), a capacitor electrode disposed on the same layer as the first lower gate electrode and spaced apart from the first lower gate electrode (Claim 1); an upper gate insulating layer disposed between the capacitor electrode and the base substrate (Claim 1); and a second gate electrode disposed between the upper gate insulating layer and the base substrate, wherein the second gate electrode overlaps the capacitor electrode (Claim 1), wherein: the lower interlayer insulating layer includes a first lower interlayer insulating layer and a second lower interlayer insulating layer (Claim 1), the first lower interlayer insulating layer is disposed between the first lower gate electrode and the second lower interlayer insulating layer, and the second lower interlayer insulating layer is disposed between the first lower interlayer insulating layer and the oxide semiconductor layer (Claim 1), the upper interlayer insulating layer includes a first upper interlayer insulating layer, a second upper interlayer insulating layer, and a third upper interlayer insulating layer (Claim 1), each of the second upper interlayer insulating layer and the third upper interlayer insulating layer includes silicon nitride (Claim 1), and a hydrogen concentration in the second upper interlayer insulating layer is less than a hydrogen concentration in the third upper interlayer insulating layer (Claim 1), and Patent No.: US 12,027,527 B2 does not explicitly disclose a hydrogen concentration in the first upper interlayer insulating layer is less than the hydrogen concentration in the second upper interlayer insulating layer.
However, Jung et al., at least implicitly, discloses
a hydrogen concentration in the first upper interlayer insulating layer is less than the hydrogen concentration in the second upper interlayer insulating layer (Par. 0053-0065 – this prior art teaches that silicon oxide, the material for the first upper insulating layer, is deposited using a “mixing gas including SiH4 and N2O, … SiH4 is a source gas of Si, and N2O is a source gas of O”; now the silicon nitride or the silicon oxynitride, the material for the second or third upper insulating layer, is deposited using a “SiH4, N2O, and NH3,
SiH4, N2O, and NH3 are source gases of Si, O, and N, respectively”; in other words, first upper insulating layer is formed without using NH3 gas, whereas the second and third upper interlayer insulating layers are formed using NH3 gas as one of the reactant gas; it is implied in this prior art and also is well-known that NH3 gas is the prominent source of hydrogen incorporation in the growing layer; because the first upper interlayer insulating layer is deposited without NH3 gas, it will have lower hydrogen concentration than the second or third upper interlayer insulating layers which are deposited using NH3 gas) It would have been obvious to one having ordinary skill in the art at the time the invention was filed to use the teachings of Jung et al. to adapt a display device, comprising: a hydrogen concentration in the first upper interlayer insulating layer of Patent No.: US 12,027,527 B2 is less than the hydrogen concentration in the second upper interlayer insulating layer in order to make sure that the channel layer is not deteriorated by the influx of hydrogen from the porous silicon oxide layer.
Regarding Claim 2, modified Patent No.: US 12,027,527 B2, as applied to claim 1, discloses
the display device, wherein the hydrogen concentration in the first upper interlayer insulating layer is less than the hydrogen concentration in the third upper interlayer insulating layer (please see the rejection of claim 1).
Regarding Claim 3, modified Patent No.: US 12,027,527 B2, as applied to claim 1, discloses
the display device, wherein the first upper interlayer insulating layer has a thickness from 500 Å to 3000 Å.(Claim 1)
Regarding Claim 4, modified Patent No.: US 12,027,527 B2, as applied to claim 1, discloses
the display device, further comprising: wherein the first lower interlayer insulating layer contacts the first lower gate electrode, and the first lower gate electrode overlaps the first upper gate electrode (Claim 1)
.
Regarding Claim 5, modified Patent No.: US 12,027,527 B2, as applied to claim 1, discloses
the display device, wherein: the oxide semiconductor layer includes a first channel region, a first drain region located at one side of the first channel region, and a first source region located at the other side of the first channel region (Claim 4); the first gate insulating layer is disposed on the first channel region of the oxide semiconductor layer and overlaps the first channel region of the oxide semiconductor layer and exposes upper surfaces of the first drain region and first source region of the oxide semiconductor layer (Claim 4); and the upper interlayer insulating layer covers the first upper gate electrode, the first gate insulating layer, and an upper surface of the oxide semiconductor layer exposed by the first source region and the first drain region (Claim 4).
Regarding Claim 6, modified Patent No.: US 12,027,527 B2, as applied to claim 5, discloses
the display device, wherein the first upper interlayer insulating layer directly contacts the first upper gate electrode, the first gate insulating layer, and the upper surface of the oxide semiconductor layer (Claim 5).
Regarding Claim 7, modified Patent No.: US 12,027,527 B2, as applied to claim 1, discloses
the display device, wherein the second upper interlayer insulating layer is disposed between the first upper interlayer insulating layer and the third upper interlayer insulating layer (Claim 6).
Regarding Claim 8, modified Patent No.: US 12,027,527 B2, as applied to claim 7, discloses
the display device, wherein: the second upper interlayer insulating layer is disposed directly on the first upper interlayer insulating layer, and the third upper interlayer insulating layer is disposed directly on the second upper interlayer insulating layer (Claim 7).
Regarding Claim 9, modified Patent No.: US 12,027,527 B2, as applied to claim 1, discloses
the display device, wherein the hydrogen concentration in the second upper interlayer insulating layer is 1E+22 atoms/cm3 or less (Claim 8). .
Regarding Claim 10, modified Patent No.: US 12,027,527 B2, as applied to claim 1, discloses
the display device, further comprising: a first source electrode or a first drain electrode disposed on the upper interlayer insulating layer (Claim 9), wherein the first source electrode is connected to the oxide semiconductor layer through a first contact hole that penetrates the upper interlayer insulating layer (Claim 9), or the first drain electrode is connected to the oxide semiconductor layer through a second contact hole that penetrates the upper interlayer insulating layer (Claim 9).
Regarding Claim 11, modified Patent No.: US 12,027,527 B2, as applied to claim 10, discloses
the display device, further comprising: a first connection electrode disposed on the upper interlayer insulating layer (Claim 10), wherein the first connection electrode is disposed on the same layer as the first source electrode (Claim 10), and the first connection electrode is connected to the first upper gate electrode through a third contact hole that penetrates the upper interlayer insulating layer (Claim 10).
Regarding Claim 12, modified Patent No.: US 12,027,527 B2, as applied to claim 10, discloses
the display device, wherein the first lower gate electrode overlaps the first upper gate electrode (Claim 11).
Regarding Claim 13, modified Patent No.: US 12,027,527 B2, as applied to claim 12, discloses
the display device, wherein the first lower interlayer insulating layer includes silicon nitride, and the second lower interlayer insulating layer contains silicon oxide (Claim 12).
Regarding Claim 14, modified Patent No.: US 12,027,527 B2, as applied to claim 1, discloses
the display device, further comprising: a lower gate insulating layer disposed between the second gate electrode and the base substrate (Claim 13); and a polycrystalline silicon semiconductor layer disposed between the lower gate insulating layer and the base substrate (Claim 13), wherein the polycrystalline silicon semiconductor layer includes a second channel region that overlaps the second gate electrode (Claim 13).
Regarding Claim 15, modified Patent No.: US 12,027,527 B2, as applied to claim 14, discloses
the display device, further comprising: a second source electrode or a second drain electrode disposed on the same layer as the first source electrode (Claim 14), wherein the second source electrode is connected to the polycrystalline silicon semiconductor layer through a fourth contact hole that penetrates the upper interlayer insulating layer, the lower interlayer insulating layer, the upper gate insulating layer, and the lower gate insulating layer (Claim 14), or the second drain electrode is connected to the polycrystalline silicon semiconductor layer through a fifth contact hole that penetrates the upper interlayer insulating layer, the lower interlayer insulating layer, the upper gate insulating layer, and the lower gate insulating layer (Claim 14).
Regarding Claim 16, modified Patent No.: US 12,027,527 B2, as applied to claim 15, discloses
the display device, wherein the polycrystalline silicon semiconductor layer, the second gate electrode, the capacitor electrode, and at least one of the second source electrode and the second drain electrode constitute a driving transistor (Claim 15).
Regarding Claim 17, modified Patent No.: US 12,027,527 B2, as applied to claim 1, discloses
the display device, wherein the lower interlayer insulating layer further includes a third lower interlayer insulating layer disposed between the first lower interlayer insulating layer and the first lower gate electrode, the third lower interlayer insulating layer includes silicon nitride, and a hydrogen concentration in the third lower interlayer insulating layer is less than a hydrogen concentration in the first lower interlayer insulating layer (Claim 16).
Regarding Claim 18, modified Patent No.: US 12,027,527 B2, as applied to claim 1, discloses
the display device, wherein the lower interlayer insulating layer further includes a third lower interlayer insulating layer disposed between the first lower interlayer insulating layer and the second lower interlayer insulating layer, the third lower interlayer insulating layer includes silicon nitride, and a hydrogen concentration in the third lower interlayer insulating layer is less than a hydrogen concentration in the first lower interlayer insulating layer (Claim 17).
Regarding Claim 19, modified Patent No.: US 12,027,527 B2, as applied to claim 1, discloses
the display device, wherein the upper interlayer insulating layer further includes a fourth upper interlayer insulating layer disposed between the second upper interlayer insulating layer and the third upper interlayer insulating layer, the fourth upper interlayer insulating layer includes silicon nitride, and a hydrogen concentration in the fourth upper interlayer insulating layer is between the hydrogen concentration in the second upper interlayer insulating layer and the hydrogen concentration in the third upper interlayer insulating layer (Claim 18).
Regarding Claim 20, modified Patent No.: US 12,027,527 B2, as applied to claim 9, discloses
the display device, wherein the upper interlayer insulating layer further includes a fourth upper interlayer insulating layer disposed between the third upper interlayer insulating layer and the first source electrode, and a hydrogen concentration in the fourth upper interlayer insulating layer is less than the hydrogen concentration in the third upper interlayer insulating layer (Claim 19).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Yoshitani et al. (Pub. No.: US 2018/0130910 A1) – This prior art teaches display device, comprising: a base substrate (110); a lower interlayer insulating layer (115) disposed on the base substrate (110); a first lower gate electrode disposed between the base substrate and the lower interlayer insulating layer; an oxide semiconductor layer (140) disposed on the lower interlayer insulating layer (115); a first gate insulating layer (150) disposed the oxide semiconductor layer (140); a first upper gate electrode (160) disposed on the first gate insulating layer (150); and an upper interlayer insulating layer (170) disposed on the first upper gate electrode (160), wherein the first upper gate electrode (160) is interposed between the oxide semiconductor layer (140) and the upper interlayer insulating layer (170), a capacitor electrode (120/145); wherein: the lower interlayer insulating layer includes a first lower interlayer insulating layer and a second lower interlayer insulating layer (Par. 0059), the second lower interlayer insulating layer is disposed between the first lower interlayer insulating layer and the oxide semiconductor layer (Par. 0059), the upper interlayer insulating layer (147) includes a first upper interlayer insulating layer (171), a second upper interlayer insulating layer (172), and a third upper interlayer insulating layer (173) (Fig. 4).
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06/08/2026
/SYED I GHEYAS/Primary Examiner, Art Unit 2893
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