Prosecution Insights
Last updated: October 24, 2026
Application No. 18/676,609

DISPLAY DEVICE AND METHOD OF PROVIDING THE SAME

Non-Final OA §102§103
Filed
May 29, 2024
Priority
Jul 11, 2023 — RE 10-2023-0090021
Examiner
DAS, PINAKI
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Display Co., Ltd.
OA Round
1 (Non-Final)
88%
Grant Probability
Favorable
1-2
OA Rounds
1y 2m
Est. Remaining
86%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allowance Rate
49 granted / 56 resolved
+19.5% vs TC avg
Minimal -2% lift
Without
With
+-1.9%
Interview Lift
resolved cases with interview
Typical timeline
3y 7m
Avg Prosecution
35 currently pending
Career history
100
Total Applications
across all art units

Statute-Specific Performance

§103
46.8%
+6.8% vs TC avg
§102
28.1%
-11.9% vs TC avg
§112
23.5%
-16.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 56 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Invention I, Species I, Sub-species I and claims 1-7, 9-10 and 12-14 in the reply filed on 9/15/2026 is acknowledged. Claims 8, 11 and 15-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention and species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 9/15/2026. Claim 9 is further withdrawn from consideration pursuant to 37 CFR 1.142(b) as being drawn to nonelected Sub-species II (as shown in Fig. 8A). Claim 9 recites the limitation wherein, “wherein the bridge electrode has an upper surface (top surface of BNEa, Fig. 8A) which is closest to the upper surface of the insulation layer (top surface of 50+60, Fig. 8A); a portion of the side surface which is between the upper surface of the insulation layer and the upper surface of the bridge electrode is exposed to outside the bridge electrode (portion of side surface of 60 that is exposed from the bridge electrode BNEa, see Fig. 8A); and the first connection electrode (CNE1a, Fig. 8A) directly contacts the upper surface of the bridge electrode and the portion of the side surface which is exposed to outside the bridge electrode (CNE1a directly contacts the top surface of bridge electrode BNEa and the exposed side surface of 60, see Fig. 8A).” In the elected Sub-species I (Fig. 7), insulation layer (50+60, Fig. 7) has an upper surface (top surface of 50+60) and a side surface (side surface of 50+60) as required in claim 9, but the side surface is never exposed (see Fig. 7) and the connection electrode (CNE1, Fig. 7) never directly contacts the side surface of the insulation layer (side surfaces of 50+60, Fig. 7). Information Disclosure Statement Acknowledgement is made of Applicant's Information Disclosure Statement (IDS) from PTO-1449. The IDS has been considered. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-2 and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cho et al. (US 2019/0115407 A1). Re Claim 1, Cho teaches a display device (Fig. 3B) comprising: a circuit layer (DP-CL, Fig. 3B, para [0039]); and a light emitting element (OLED, Fig. 3B, para [0039]) which is on the circuit layer and connected thereto (see Fig. 3B), wherein the circuit layer (DP-CL) comprises: a transistor (T1, Fig. 3B, para [0039]); an insulation layer (10+20+30+40, Fig. 3B, paras [0047], [0049] and [0051]) on the transistor (T1), the insulation layer (10+20+30+40) comprising: a side surface which defines a contact-hole of the insulation layer (side surface of 10+20+30+40 defines the contact-hole CH2, see Fig. 3B, para [0057]) at which a portion of the transistor is exposed to outside the insulation layer (portion of transistor T1 is exposed to the contact-hole CH2), and an upper surface (top surface of 10+20+30+40) from which the side surface extends (see Fig. 3B); a bridge electrode (SE1, Fig. 3B, para [0057]) which extends along the side surface of the insulation layer (side surface of 10+20+30+40, Fig. 3B) and contacts the portion of the transistor which is exposed to outside the insulation layer (SE1 contacts T1, see Fig. 3B); and a connection electrode (CNE, Fig. 3B, para [0060]) which connects to the transistor (electrically connects to T1, Fig. 3B), the connection electrode comprising a first connection electrode (CNE, Fig. 3B) which is directly on the bridge electrode (SE1, see Fig. 3B) and spaced apart from the portion of the transistor (CNE is spaced apart from T1, see Fig. 3B) which is exposed to outside the insulation layer. Re Claim 2, Cho teaches the display device of claim 1, wherein the transistor comprises (T1, Fig. 3B) a semiconductor layer (OSP1, para [0046], Cho) which defines the portion of the transistor which is exposed to outside the insulation layer (Fig. 3B). Re Claim 10, Cho teaches the display device of claim 1, wherein the insulation layer (10+20+30+40, Fig. 3B) further comprises: a first insulation layer (10, Fig. 3B) on the transistor (T1, Fig. 3B); and a second insulation layer (20) on the first insulation layer (10), and the contact-hole (contact-hole CH2, Fig. 3B) passes through the first insulation layer and the second insulation layer (see Fig. 3B). Rejection 2 Claim Rejections - 35 USC § 102 Claims 1-3, 7, 10 and 13-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US 2017/0098718 A1). Re Claim 1, Kim teaches a display device (Fig. 11) comprising: a circuit layer (circuit layer containing TFT, Fig. 11, para [0043]); and a light emitting element (EL, Fig. 11, para [0086]) which is on the circuit layer and connected thereto (see Fig. 11), wherein the circuit layer comprises: a transistor (TFT, Fig. 11, para [0043]); an insulation layer (13+15, Fig. 11, para [0046]) on the transistor (TFT), the insulation layer (13+15) comprising: a side surface which defines a contact-hole of the insulation layer (side surface of 13+15 defines the contact-hole H2, see Figs. 4 and 11, para [0059]) at which a portion of the transistor is exposed to outside the insulation layer (portion of transistor TFT is exposed to the contact-hole H2, see Figs. 4 and 11), and an upper surface (top surface of 13+15) from which the side surface extends (see Figs. 4 and 11); a bridge electrode (29a, Fig. 11, paras [0046] – [0049]) which extends along the side surface of the insulation layer (side surface of 13+15, Fig. 11) and contacts the portion of the transistor which is exposed to outside the insulation layer (29a contacts TFT, see Fig. 11); and a connection electrode (27+29b, Fig. 11, paras [0046] – [0049]) which connects to the transistor (electrically connects to TFT, Fig. 11), the connection electrode comprising a first connection electrode (27, Fig. 11) which is directly on the bridge electrode (29a, see Fig. 11) and spaced apart from the portion of the transistor (27 is spaced apart from TFT, see Fig. 11) which is exposed to outside the insulation layer. Re Claim 2, Kim teaches the display device of claim 1, wherein the transistor comprises (TFT, Fig. 11) a semiconductor layer (21, Fig. 11, para [0046]) which defines the portion of the transistor which is exposed to outside the insulation layer (see Fig. 11). Re Claim 3, Kim teaches the display device of claim 3, wherein the semiconductor layer (21, Fig. 11) includes an upper surface at which the semiconductor layer is exposed to outside the insulation layer (upper surface of 21 is exposed at the contact hole H2, Fig. 11), and the connection electrode (27+29b, Fig. 11) further comprises a second connection electrode (29b, Fig. 11) on the upper surface of the semiconductor layer (21, see Fig. 11). Re Claim 7, Kim teaches the display device of claim 3, wherein the bridge electrode (29a, lightly doped polysilicon, para [0063]) comprises a material different from a material of each of the first connection electrode (27, Fig. 11, can be Titanium layer, para [0076], note that layer 26 is patterned to form layer 27, see Figs. 7-8) and of the second connection electrode (29b, heavily doped polysilicon, para [0068]). Re Claim 10, Kim teaches the display device of claim 1, wherein the insulation layer (13+15, Fig. 11) further comprises: a first insulation layer (13, Fig. 11) on the transistor (TFT, Fig. 11); and a second insulation layer (15) on the first insulation layer (13), and the contact-hole (H2, Figs. 4 and 11) passes through the first insulation layer and the second insulation layer (see Figs. 4 and 11). Re Claim 13, Kim teaches the display device of claim 1, wherein the bridge electrode (29a, Fig. 11) comprises an n-type dopant (29a can include n-type dopants, para [0063]). Re Claim 14, Kim teaches the display device of claim 1, wherein the circuit layer (circuit layer containing TFT, Fig. 11) further comprises an organic layer (17, Fig. 11, para [0087]) which is on the insulation layer (13+15, Fig. 11) and comprises a side surface defining an upper contact-hole of the organic layer (side surface of 17 defines a contact-hole where electrode 30 is formed, see Fig. 11) at which a portion of the first connection electrode (27, Fig. 11) is exposed to outside the organic layer (portion of 27 is exposed in the contact-hole where 30 is formed, see Fig. 11). Rejection 3 Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-2 are rejected under 35 U.S.C. 103 as being unpatentable over Cho et al. (US 2019/0115407 A1), and further in view of Bao et al. (US 2021/0265478 A1). Re Claim 1, Cho teaches a display device (Fig. 3B) comprising: a circuit layer (DP-CL, Fig. 3B, para [0039]); and a light emitting element (OLED, Fig. 3B, para [0039]) which is on the circuit layer and connected thereto (see Fig. 3B), wherein the circuit layer (DP-CL) comprises: a transistor (T1, Fig. 3B, para [0039]); an insulation layer (10+20+30+40, Fig. 3B, paras [0047], [0049] and [0051]) on the transistor (T1), the insulation layer (10+20+30+40) comprising: a side surface which defines a contact-hole of the insulation layer (side surface of 10+20+30+40 defines the contact-hole CH2, see Fig. 3B, para [0057]) at which a portion of the transistor is exposed to outside the insulation layer (portion of transistor T1 is exposed to the contact-hole CH2), and an upper surface (top surface of 10+20+30+40) from which the side surface extends (see Fig. 3B); a connection electrode (SE1, Fig. 3B, para [0057]) which connects to the transistor (T1, Fig. 3B), the connection electrode comprising a first connection electrode (SE1, Fig. 3B). Cho does not disclose a bridge electrode and hence does not disclose the following: a bridge electrode which extends along the side surface of the insulation layer and contacts the portion of the transistor which is exposed to outside the insulation layer; and the connection electrode comprising a first connection electrode which is directly on the bridge electrode and spaced apart from the portion of the transistor which is exposed to outside the insulation layer. Related art Bao teaches a contact electrode structure (4+6, Fig. 5, paras [0038] – [0040]) on a transistor (active layer 2 with gate 7, Figs. 5 and 7, para [0057]) used in a display device, where the contact electrode structure (4+6, Fig. 5) consists of a connection electrode (4, Fig. 5, similar to connection electrode of Cho) and a bridge electrode (6, Fig. 5). The bridge electrode is a titanium silicide layer (para [0044]) which reduces the contact resistance between the active layer of the transistor and the metal portion of the connection electrode (paras [0037] – [0044]), thus improving the signal quality of the device. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to modify the device of Cho such that it includes a bridge electrode as taught by Bao, since the bridge electrode helps in reducing the contact resistance between the active layer of the transistor and the metal portion of the connection electrode (paras [0037] – [0044], Bao), thus improving the signal quality of the device. Thus, Cho modified by Bao teaches: a bridge electrode (6, Fig. 5, Bao) which extends along the side surface of the insulation layer (side surface of 32+33, Fig. 5, Bao, similar to side surface of 10+20+30+40 defining the contact-hole CH2, Fig. 3B of Cho) and contacts the portion of the transistor (layer 6 contacts the transistor active layer 2, Fig. 5, Bao) which is exposed to outside the insulation layer; and the connection electrode (4, Fig. 5, Bao, similar to SE1, Fig. 3B of Cho) comprising a first connection electrode (4, Fig. 5, Bao) which is directly on the bridge electrode (6, Fig. 5, Bao) and spaced apart from the portion of the transistor which is exposed to outside the insulation layer (electrode 4 is spaced apart from the active layer 2 of the transistor, Fig. 5, Bao). Re Claim 2, Cho modified by Bao teaches the display device of claim 1, wherein the transistor comprises (T1, Fig. 3B, Cho) a semiconductor layer (OSP1, para [0046], Cho) which defines the portion of the transistor which is exposed to outside the insulation layer (see Fig. 3B). Claims 3-4 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Cho et al. (US 2019/0115407 A1) and Bao et al. (US 2021/0265478 A1), and further in view of Choi et al. (US 2008/0197770 A1). Re Claim 3, Cho modified by Bao teaches the display device of claim 2, wherein the semiconductor layer (OSP1, Fig. 3B, Cho) includes an upper surface at which the semiconductor layer is exposed to outside the insulation layer (upper surface of OSP1 is exposed at the contact hole CH2, Fig. 3B, Cho). Cho modified by Bao does not explicitly teach that the connection electrode (SE1, Fig. 3B, Cho) further comprises a second connection electrode on the upper surface of the semiconductor layer. However, in a related art Choi teaches (para [0023], Choi) that the source/drain connection electrode can be made of a single metal layer (like SE1, Fig. 3B of Cho) or a stacked multilayer film (like electrode 4, Fig. 5 of Bao). Bao discloses that the connection electrode (4, Fig. 5, Bao) is a multilayer stack (upper 41 + 42 + lower 41, Fig. 5, para [0045]) made of a first connection electrode (upper 41, Fig. 5) and a second connection electrode (lower 41, Fig. 5) on the upper surface of the transistor (see Fig. 5, Bao). It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, such that the connection electrode of Cho modified by Bao can be a multilayer stack as shown by Bao instead of a single metal layer as shown by Cho, because these are art-recognized alternate structures for source/drain electrodes as disclosed by Choi (para [0023]). The use of a known structure for making source/drain electrodes to yield predictable results is prima facie obvious. Also see KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007). Re Claim 4, Cho modified by Bao and Choi teaches the display device of claim 3, wherein the second connection electrode (lower 41, Fig. 5, Bao) is spaced apart from the first connection electrode (upper 41, Fig. 5, Bao), along the bridge electrode (6, Fig. 5, Bao); and the second connection electrode is electrically connected to the first connection electrode via the bridge electrode (see Fig. 5, Bao). Re Claim 7, Cho modified by Bao and Choi teaches the display device of claim 3, wherein the bridge electrode (6, titanium silicide layer, Fig. 5, para [0044], Bao) comprises a material different from a material of each of the first connection electrode (upper 41, titanium layer, Fig. 5, para [0045], Bao) and of the second connection electrode (lower 41, titanium layer, Fig. 5, para [0045], Bao). Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Cho et al. (US 2019/0115407 A1), Bao et al. (US 2021/0265478 A1) and Choi et al. (US 2008/0197770 A1), and further in view of Won et al. (US 2018/0151633 A1). Re Claim 5, Cho modified by Bao and Choi teaches the display device of claim 4, but does not disclose a width of the contact-hole is about 0.5 micrometer to about 2 micrometers. However, in a related semiconductor art, Won teaches that the width of contact-holes can be 1.5 micrometer (para [0051]). It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to use a known width for the contact-holes as that would simplify the manufacturing process. The use of a known contact-hole width for its known purpose of making source/drain contacts is prima facie obvious. Also see KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007). Re Claim 6, Cho modified by Bao and Choi teaches the display device of claim 4, but does not disclose that a depth of the contact-hole is about 1 micrometer to about 1.5 micrometer. However, in a related semiconductor art, Won teaches that the depth of contact-holes can be 1.2 micrometer (para [0051]). It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to use a known depth for the contact-holes as that would simplify the manufacturing process. The use of a known contact-hole depth for its known purpose of making source/drain contacts is prima facie obvious. Also see KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007). Allowable Subject Matter Claim 12 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Claim 12 is allowable for at least the reasons of, “the first connection electrode comprises portions which extend from the upper surface of the insulation layer and along the side surface thereof, the portions being spaced apart from each other to define an upper hole in the first connection electrode, and a size of the upper hole increases in a direction from the upper surface of the insulation layer to the portion of the transistor which is exposed to outside the insulation layer.” Related art Bao (see rejection 3 above) teaches the first connection electrode (4, Fig. 5, Bao) comprises portions which extend from the upper surface of the insulation layer and along the side surface thereof (left and right portions of 4, see annotated Fig. 5 of Bao below), the portions being spaced apart from each other to define an upper hole in the first connection electrode (marked “upper hole” in annotated Fig. 5 below). However, the hole tapers in the opposite direction than the one recited in the claim and hence Bao does not teach that the “size of the upper hole increases in a direction from the upper surface of the insulation layer to the portion of the transistor which is exposed to outside the insulation layer”. PNG media_image1.png 349 672 media_image1.png Greyscale Related art Im et al. (US 2021/0202651 A1) teaches an electrode structure (electrode layer 7, Fig. 2, para [0080]) within a trench (trench T1, Fig. 2), formed between different pixel areas (compare Figs. 1 and 2), where the electrode (7, Fig. 2) has portions on either side of the trench (trench T1, Fig. 2) that define a hole (see Fig. 2) whose size increases in the direction from the top surface of the trench to the bottom of the trench (see Fig. 2), similar to the limitation recited in claim 12. However, in the Examiner’s opinion, it would not be obvious to one of ordinary skill to combine the teachings of Im and Bao to reach the entire limitation of claim 12, when taken in context of the independent claim 1, as a whole. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to PINAKI DAS whose telephone number is (703)756-5641. The examiner can normally be reached M-F 8-5 EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JULIO MALDONADO can be reached at (571)272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /P.D./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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Prosecution Timeline

May 29, 2024
Application Filed
Oct 15, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
88%
Grant Probability
86%
With Interview (-1.9%)
3y 7m (~1y 2m remaining)
Median Time to Grant
Low
PTA Risk
Based on 56 resolved cases by this examiner. Grant probability derived from career allowance rate.

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