DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-16,18,19 is/are rejected under 35 U.S.C. 102(a1) as being anticipated by Yang US 2023/0157036.
Regarding claim 1, Yang shows in FIG. 2, and discloses a semiconductor device, comprising: a substrate (100)[0033]; a bottom insulating layer (102)[0033] positioned on the substrate (100); a bit line contact structure comprising: a bit line contact (DC) [0027] positioned penetrating the bottom insulating layer (102) and extending to the substrate (100), with two parallel first sides along a first direction in a top-view perspective, and two parallel second sides along a second direction perpendicular to the first direction; and two contact-isolating spacers (141)[0028] positioned on the two first sides of the bit line contact; and a bit line structure (131,132)[0026] positioned on the bit line contact structure (DC) and on the bottom insulating layer (102) and extending along the first direction in a top-view perspective.
Regarding claim 2, Yang shows in FIG. 2, and discloses a semiconductor device, wherein a width of the two contact-isolating spacers (141) and a width of the bit line contact (DC) are substantially the same.
Regarding claim 3, Yang shows in FIG. 2, and discloses a semiconductor device, wherein a width of the bit line contact structure (DC) and a width of the bit line structure (131,132) are substantially the same.
Regarding claim 4, Yang shows in FIG. 2, and discloses a semiconductor device, further comprising a common source region (112a) positioned in the substrate (100), wherein the bit line contact (DC) penetrates the bottom insulating layer (102) and extends to the common source region (112a).
Regarding claim 5, Yang shows in FIG. 2, and discloses a semiconductor device, further comprising two word line structures (WL) [0026] positioned in the substrate (100), parallel to each other with the common source region (112) in between, and extending along the second direction in a top-view perspective.
Regarding claim 6, Yang shows in FIG. 2, and discloses a semiconductor device, wherein the bit line structure comprises: a bit line bottom conductive layer (131) positioned on the bit line contact structure (DC) and the bottom insulating layer (102); a bit line top conductive layer (132) [0055] positioned on the bit line bottom conductive layer; and a bit line capping layer (137)[0055] positioned on the bit line top conductive layer.
Regarding claim 7, Yang shows in FIG. 2, and discloses a semiconductor device, further comprising two spacer structures (SPS)(21,23,25, on each side)[0032] positioned on the bottom insulating layer (102) and covering sides of the bit line structure (131,132).
Regarding claim 8, Yang shows in FIG. 2, and discloses a semiconductor device, wherein the two spacer structures (SPS)[0032] respectively comprises: an inner spacer (25) covering the side of the spacer structure; a middle spacer (23) covering the inner spacer; and an outer spacer (21) covering the middle spacer.
Regarding claim 9, Yang shows in FIG. 2, and discloses a semiconductor device, further comprising two cell contact layers (BC)[0029] positioned adjacent to the two spacer structures (SPS), separated from each other with the bit line structure (131,132) in between, penetrating the bottom insulating layer, and extending to the substrate.
Regarding claim 10, Yang shows in FIG. 2, and discloses a semiconductor device, further comprising two drain regions (112b) positioned in the substrate (100), wherein the two drain regions (112b) are separated from each other with the common source region (112a) in between, and the two cell contact layers are positioned on the two drain regions.
Regarding claim 11, Yang shows in FIG. 2, and discloses a semiconductor device, wherein the middle spacer comprises silicon oxide [0032].
Regarding claim 12, Yang shows in FIG. 2, and discloses a semiconductor device, wherein the inner spacer and the outer spacer comprise the same material [0032].
Regarding claim 13, Yang shows in FIG. 2, and discloses a semiconductor device, wherein the bit line bottom conductive layer (131) comprises doped polycrystalline silicon, doped polycrystalline germanium, doped polycrystalline silicon germanium, or a combination thereof [0055].
Regarding claims 14,15, Yang shows in FIG. 2, and discloses a semiconductor device, wherein the bit line top conductive layer (132) comprises titanium, nickel, platinum, tantalum, cobalt, silver, copper, or aluminum [0055]; wherein the bit line contact comprises tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides, metal nitrides, transition metal aluminides, or a combination thereof [0055].
Regarding claim 16, Yang shows in FIG. 2, and discloses a semiconductor device, wherein the contact-isolating spacers (141) comprise silicon nitride [0028].
Regarding claim 18, Yang shows in FIG. 2, and discloses a semiconductor device, further comprising two buried insulating layers (SPS) covering the two contact-isolating spacers (141).
Regarding claim 19, Yang shows in FIG. 2, and discloses a semiconductor device, wherein a height of the two contact-isolating spacers (141) is less than a height of the two buried insulating layers (SPS).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang.
Regarding claim 17, Yang shows in FIG. 2, and discloses a semiconductor device, a ratio of a width of the two contact-isolating spacers (141) to a width of the bit line contact (DC).
As for the ratio being between about 0.90 and 1.00, Applicant did not show criticality of the particular optimum value of the ratio. To establish unexpected results over a claimed range or optimum value, applicants should compare a sufficient number of tests both inside and outside the claimed range to show the criticality of the claimed range. In re Hill, 284 F.2d 955, 128 USPQ 197 (CCPA 1960).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARC-ANTHONY ARMAND whose telephone number is (571)272-5178. The examiner can normally be reached 8am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven B Gauthier can be reached at 571-270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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MARC - ANTHONY ARMAND
Primary Examiner
Art Unit 2813
/MARC-ANTHONY ARMAND/ Primary Examiner, Art Unit 2813
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