DETAILED ACTION
This Office Action is in response to the applicant's application filed May 29th, 2024. In virtue of this communication, claims 1-20 are currently presented in the instant application.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cheng et al. (US 2022/0384496 A1; hereinafter Cheng).
With respect to claim 1, Cheng teaches an image sensor 134 in at least Fig. 5 with Figs. 1-2D, 4, and 6-21 teaching overlapping subject matter comprising:
a photodetector 104 in a semiconductor substrate 102’ (see Figs. 5-10 and paragraphs 16, 17, 29, 32);
a floating node 204 in the semiconductor substrate 102’ and beside the photodetector 104 (see Figs. 5-8 and paragraphs 27, 34);
a transfer gate 202 over and between the photodetector 104 and the floating node 204 (see Figs. 5-8 and paragraphs 27, 29, 34);
a deep trench isolation (DTI) structure 111 extending into the semiconductor substrate 102’ from a backside 124 of the semiconductor substrate 102’ (see Figs. 2A-2D, 5, 12-16, and paragraphs 16, 17, 29, 38, 42; note BDTI is back-side deep trench isolation); and
a shallow trench isolation (STI) structure 402 extending into the semiconductor substrate 102’ from a frontside 122 of the semiconductor substrate 102’ and over the DTI structure 111 (see Figs. 5, 6, 12-16, and paragraphs 28, 32, 38; 111 extends into 402),
wherein the DTI 111 structure extends into the semiconductor substrate 102’ to a first depth (from 124 to 122) from the backside 124, and wherein the DTI structure 111 extends into the STI structure 402 to a second depth (from 124 to interface of 111 with 402 but not to 122) from the backside 124 different than the first depth (see Figs. 1-2D, 5, 6, 12-16, and paragraphs 16, 17, 29, 38, 42).
With respect to claim 2, Cheng teaches the image sensor of claim 1, wherein the DTI structure 111 has an upper surface (sidewall of 111 within 402) at the second depth (from 124 to interface of 111 with 402 but not to 122), wherein the second depth (from 124 to interface of 111 with 402 but not to 122) is less than a thickness of the semiconductor substrate 102’, and wherein a lower surface of the STI structure 402 is on the upper surface (sidewall of 111 within 402) of the DTI structure 111 (see Fig. 5 and paragraphs 16, 17, 29, 38, 42).
With respect to claim 3, Cheng teaches the image sensor of claim 1, wherein the DTI structure 111 has an upper surface at the first depth (from 124 to 122), and wherein the first depth is approximately equal to a thickness of the semiconductor substrate 102’ and the upper surface extends along the frontside 122 of the semiconductor substrate 102’ beside the STI structure 402 (see Fig. 5 and paragraphs 16, 17, 29, 38, 42).
With respect to claim 4, Cheng teaches the image sensor of claim 1, further comprising: an isolation region 110 in the semiconductor substrate 102’ and beside the STI structure 402, the isolation region 110 extending from the frontside 122 of the semiconductor substrate 102’ toward the backside 124 of the semiconductor substrate 102’ and surrounding the photodetector 104, wherein the DTI 111 structure extends into the isolation region 110 to the first depth from the backside (from 124 to 122) (see Fig. 5 and paragraphs 24, 25, 28, 33).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8, 9, 13, 16, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al. (US 2022/0384496 A1; hereinafter Cheng) in view of Tsai et al. (US 2022/0320154 A1; hereinafter Tsai).
With respect to claim 8, Cheng discloses an image sensor 134 in at least Fig. 5 with Figs. 1-2D, 4, and 6-21 teaching overlapping subject matter comprising:
a semiconductor substrate 102’, a bulk region 128 of the semiconductor substrate 102’ having a first doping type (p-type), a photodetector region 104 of the semiconductor substrate 102’ having a second doping type (n-type) different than the first doping type (p-type), a floating region 204 of the semiconductor substrate 102’ and extending from a frontside 122 of the semiconductor substrate 102’ toward a backside 124 of the semiconductor substrate 102’ (see Figs. 5-10 and paragraphs 16, 17, 27, 29, 32-34);
a transfer gate 202 along the frontside 122 of the semiconductor substrate 103’, the transfer gate 202 being over and between the photodetector region 104 and the floating region 204 (see Figs. 5-8 and paragraphs 27, 29, 34);
a deep trench isolation (DTI) structure 111 extending into the semiconductor substrate 102’ from the backside 124 of the semiconductor substrate 102’ toward the frontside 122 and surrounding the photodetector region 104, the DTI structure 111 having a first upper surface (bottom most surface of 111 from 124) at a first depth (from 124 toward 122) from the backside 124 of the semiconductor substrate 102’ along a first wall (a wall of 111) of the DTI structure 111, the DTI structure 111 having a second upper surface (side surface of 111 within 402 but not bottom most surface) at a second depth (from 124 toward 122) from the backside 124 of the semiconductor substrate 102’ along an intersection of the DTI structure 111 where the first wall (a wall of 111) and a second wall (another wall of 111) of the DTI structure 111 intersect, the second depth being different than the first depth (see Figs. 1-2D, 5, 6, 12-16, and paragraphs 16, 17, 29, 38, 42; note BDTI is back-side deep trench isolation; BDTI structure surrounds array of rows and columns of pixel regions); and
a shallow trench isolation (STI) structure 402 extending into the semiconductor substrate 102’ from the frontside 122 of the semiconductor substrate 102’ toward the backside 124 and over the DTI structure 111 at the intersection of the DTI structure 111, the STI structure 111 having a first lower surface (first interface of 111 with 402) at a third depth from the backside 124 of the semiconductor substrate 102’, the STI structure 402 having a second lower surface (side surface of 402 interfacing with 111) on the second upper surface (side surface of 111 within 402 but not bottom most surface) of the DTI structure 111, the third depth being less than the second depth so a lower portion of the STI structure 402 has a vertical overlap with a first upper portion (bottom most surface of 111 from 124) of the DTI structure 111 (see Figs. 1-2D, 5, 6, 12-16, and paragraphs 16, 17, 29, 38, 42; slanted lower surface of 111 has a depth at 402 from 124 that is less than another slanted lower surface of 11 at 402 from 124).
Cheng does not explicitly disclose wherein the floating region has the second doping type.
Tsai discloses an image sensor in at least Figs. 4A-4C wherein a floating region 204 has a second doping type (n-type) (see Figs. 4A-4C and paragraphs 14, 15, 20; note that the photodetector region 104 and the floating region 204 have the same doping type).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the floating region of Cheng would have the second doping type as taught by Tsai because it is well known in the art that that the floating region would have the same doping type as the photodetector region (see MPEP 2144 I).
With respect to claim 9, the combination of Cheng and Tsai discloses the image sensor of claim 8, an isolation region 110 of the semiconductor substrate 102’ having the first doping type (p-type), the isolation region 110 extending from the frontside 122 of the semiconductor substrate 102’ toward the backside 124 of the semiconductor substrate 102’ to a fourth depth from the backside 124 along the first wall (a wall of 111) of the DTI structure 111, the fourth depth being less than the first depth (at bottom most surface of 111 from 124) so a lower portion of the isolation region 110 has a vertical overlap with a second upper portion of the DTI structure 111 along the first wall of the DTI structure 111 (see Cheng: Fig. 5 and paragraphs 24, 25, 28, 33; note location where 110 and 111 are vertically overlapping).
With respect to claim 13, the combination of Cheng and Tsai discloses the image sensor of claim 8, wherein the first depth (at bottom most surface of 111 from 124) is approximately equal to a thickness of the semiconductor substrate 102’ so the first upper surface of the DTI structure 111 extends along the frontside 122 of the semiconductor substrate 102’, wherein the first lower surface of the STI structure 402 is on a third upper surface of the DTI structure 111 (see Cheng: Figs. 1-2D, 5, 6, 12-16, and paragraphs 16, 17, 29, 38, 42.
With respect to claim 16, Cheng discloses a method for forming an image sensor 134 in Figs. 5-21, the method comprising:
forming a photodetector region 104 and a floating region 204 in a semiconductor substrate 102’ along a frontside 122 of the semiconductor substrate 102’, a bulk region 128 of the semiconductor substrate 102’ having a first doping type (p-type), the photodetector region 104 having a second doping type (n-type) different than the first doping type (p-type) (see Figs. 5-10 and paragraphs 16, 17, 27, 29, 32-34);
forming a transfer gate 202 along the frontside 122 of the semiconductor substrate 102’, the transfer gate 202 being over and between the photodetector region 104 and the floating region 204 (see Fig. 5-8 and paragraphs 27, 29, 34);
etching the frontside 122 of the semiconductor substrate 102’ to form a first opening (location of 402) in the semiconductor substrate 102’ (see Fig. 6 and paragraphs 28, 32);
depositing a first dielectric (of 402) in the first opening (location of 402) to form a shallow trench isolation (STI) structure 402 in the first opening (see Fig. 6 and paragraphs 28, 32);
etching a backside 124 of the semiconductor substrate 102’ and the STI structure 402 to form a trench 1202 in the semiconductor substrate 102’ and the STI structure 402 and surrounding the photodetector region 104 (see Figs. 2A-2D, 5, 12-16 and paragraphs 20, 29, 38; 1202 extends into 402); and
depositing a second dielectric 112 in the trench 1202 to form a deep trench isolation (DTI) structure 111 in the trench (see Figs. 2A-2D, 5, and 12-16, and paragraphs 26, 42).
Cheng does not explicitly disclose wherein the floating region has the second doping type.
Tsai discloses a method for forming an image sensor in at least Figs. 4A-4C wherein a floating region 204 has a second doping type (n-type) (see Figs. 4A-4C and paragraphs 14, 15, 20; note that the photodetector region 104 and the floating region 204 have the same doping type).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the floating region of Cheng would have the second doping type as taught by Tsai because it is well known in the art that that the floating region would have the same doping type as the photodetector region (see MPEP 2144 I).
With respect to claim 19, Cheng and Tsai discloses the method of claim 16, further comprising: forming an isolation region 110 in the semiconductor substrate 102’ along the frontside 122 of the semiconductor substrate 102’, the isolation region 110 having the first doping type (p-type), wherein the etching of the backside 124 of the semiconductor substrate 102’ extends the trench extends into the isolation region 110 (see Cheng: Figs. 7-12, and paragraphs 24, 25, 28, 33).
Claims 17 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al. (US 2022/0384496 A1; hereinafter Cheng) in view of Tsai et al. (US 2022/0320154 A1; hereinafter Tsai) as applied to claim 16 above, and further in view of Wang et al. (US 2019/0088705 A1; hereinafter Wang).
With respect to claim 17, the combination of Cheng and Tsai discloses the method of claim 16.
The combination does not explicitly disclose wherein an etch rate of the STI structure is substantially less than an etch rate of the semiconductor substrate during the etching of the backside of the semiconductor substrate and the STI structure.
Wang discloses a method in Figs. 1A-1D wherein an etch rate of an STI structure 103 is substantially less than an etch rate of a semiconductor substrate 102 during an etching of a backside of the semiconductor substrate 102 and the STI structure 103 (see Figs. 1A, 1B, and paragraph 21).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that an etch rate of the STI structure of the combination of Cheng and Tsai would be substantially less than an etch rate of the semiconductor substrate during the etching of the backside of the semiconductor substrate and the STI structure as taught by Wang because it is well known in the art that the materials used for STI structures are etched at rates substantially less than those of semiconductor substrates (see MPEP 2144 I and paragraph 21 of Wang).
With respect to claim 18, the combination of Cheng, Tsai, and Wang discloses the method of claim 17, wherein the backside 124 of the semiconductor substrate 102’ and the STI structure 402 are laterally etched in a first direction to form a first trench street and laterally etched in a second direction, transverse to the first direction, to form a second trench street, and wherein the backside 124 of the semiconductor substrate and the STI structure 402 are etched so the first trench street and the second trench street intersect at the STI structure 402 (see Cheng: Figs. 4-16 and paragraphs 16, 17, 20, 28, 38; note pixel regions arranged in array of rows and columns and that 402 and 111 are vertically aligned and share a common center line 404).
Allowable Subject Matter
Claims 5-7, 10-12, 14, 15, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art does not disclose or fairly suggest:
wherein the DTI structure has an upper surface at the first depth, and wherein the isolation region is between the upper surface and the frontside of the semiconductor substrate, and wherein the isolation region extends along the upper surface and below the upper surface of the DTI structure along a first sidewall and a second sidewall of the DTI structure, as called for in claim 5;
wherein the DTI structure is spaced from the floating node under the floating node, and wherein the DTI structure extends into the semiconductor substrate to a third depth from the backside under the floating node, the third depth being less than the first depth and the second depth, as called for in claim 6 (claim 7 depends from claim 7);
wherein the first depth is less than the third depth and the semiconductor substrate is between the first upper surface of DTI structure and the first lower surface of the STI structure, as called for in claim 10;
wherein the first depth is greater than the third depth and less than the second depth so the first upper surface of the DTI structure is above the first lower surface of the STI structure and below the second upper surface of the DTI structure, and wherein the first lower surface of the STI structure is on a third upper surface of the DTI structure, as called for in claim 11;
wherein the first depth is greater than the second depth and less than a thickness of the semiconductor substrate so the first upper surface of the DTI structure is above the second upper surface of the DTI structure and below the frontside of the semiconductor substrate, wherein the first lower surface of the STI structure is on a third upper surface of the DTI structure, as called for in claim 12;
wherein the first depth is greater than a thickness of the semiconductor substrate so the first upper surface of the DTI structure is above the frontside of the semiconductor substrate, wherein the first lower surface of the STI structure is on a third upper surface of the DTI structure, as called for in claim 14;
the STI structure having a third lower surface at a fourth depth from the backside of the semiconductor substrate, the fourth depth being less than the second depth and the third depth so the third lower surface is below the first lower surface and the second lower surface of the STI structure, as called for in claim 15;
wherein the backside of the semiconductor substrate and the STI structure are etched with a first etching process and a second etching process after the first etching process, wherein a masking layer is over the floating region during the first etching process and the masking layer is removed from over the floating region during the second etching process, as called for in claim 20.
Citation of Pertinent Prior Art
The following prior art made of record and not relied upon is considered pertinent to applicant's disclosure because each reference teaches an image structure and method similar to that of the claimed invention: US 2021/0335861 A1, US 2022/0293457 A1, and US 2022/0344383 A1.
Inquiry
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JORDAN M KLEIN whose telephone number is (571)270-7544. The examiner can normally be reached 9:00 am - 5:00 pm.
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/J.M.K/Examiner, Art Unit 2893
/SUE A PURVIS/ Supervisory Patent Examiner, Art Unit 2893
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