DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 16-35 in the reply filed on 8/25/26 is acknowledged.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 16,17,19,21,22,24-29,31-33 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liaw US 2023/0033790.
Regarding claim 16, Liaw shows in FIG, 2A-16D, a method, comprising: forming a first stack (Fig. 3B,218A,[0022]) of alternating first semiconductor channel layers (Fig. 3B,215,[0022]) and first sacrificial layers (Fig. 3B,210,[0022]) over a P-well region of a substrate and a second stack (Fig. 3B,218B,[0022]) of alternating second semiconductor channel layers (Fig. 3B,215,[0022]) and second sacrificial layers (Fig. 3B,210,[0022]) over an N-well region of the substrate (Fig. 4C,4D,204B,[0029]), respectively; forming a dummy gate structure (Fig. 4A,4D, 245,[0026]) crossing the first stack of the first semiconductor channel layers (215) and the first sacrificial layers (210) and the second stack of the second semiconductor channel layers (Fig. 3B,218B,[0022]) (215) and the second sacrificial layers (210); removing the first and second sacrificial layers (210, [0020]), such that the first and second semiconductor channel layers (215) are suspended over the substrate (Fig. 7C, 7D, 215,[0020])(215 is suspended); forming a mask [0027](a mask layer is formed on one side) over the N-well region (204B) of the substrate and covering the second semiconductor channel layers, while leaving the first semiconductor channel layers over the P-well region (Fig. 4C,4D,204C,[0029]) of the substrate exposed; performing a first etching process (Fig. 7A,7D, 215,[0031])(215 suspended and etched) to narrow down the first semiconductor channel layers (215); removing the mask after the first etching process is complete (obvious step); and forming a common gate structure (Fig. 14C,14D, 350,[0042]) wrapping around the first and second semiconductor channel layers (Fig. 3B,215,[0022]).
Liaw differs from the claimed invention because he does not explicitly disclose a method of removing the mask after the first etching process is complete.
A method of removing the mask after the first etching process is complete is an obvious step when using a mask in semiconductor technology. Therefore, at the time the invention was made; It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to remove a mask used for performing an etching process. This is an obvious step a POSITA will take.
Regarding claim 17, Liaw shows in FIG, 2A-16D, a method further comprising: forming first spacers (Fig. 4C, 247, [0029]) on opposite sidewalls of the dummy gate structure (Fig. 4A,4D, 245,[0026]); forming first inner spacers (Fig. 8C, 255, [0032]) on opposite ends of each of the first sacrificial layers (Fig. 3B,210,[0022]) and second inner spacers (Fig. 8C, 255, [0032]) on opposite ends of each of the second sacrificial layers (Fig. 3B,210,[0022]); and after forming the first and second inner spacers (255), forming second spacers (Fig. 14C, 280,282, [0041] along the first spacers (247).
Regarding claim 19, Liaw shows in FIG, 2A-16D, a method wherein materials of the first and second inner spacers (Fig. 8C, 255, [0032]) have a higher dielectric constant than materials of the first and second spacers.
As for the different material, It would have been obvious to one having ordinary skill in the art at the time of the invention was made to have a specific material, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use. In re Leshin, 125 USPQ 416. MPEP 2144.07
Regarding claim 21, Liaw shows in FIG, 2A-16D, a method, comprising: forming first semiconductor channel layers (Fig. 3B,215,[0022]) and second semiconductor channel layers (Fig. 3B,215,[0022]) over a substrate (202); forming a dummy gate structure (Fig. 4A,4D, 245,[0026]) over the first semiconductor channel layers (Fig. 3B,215,[0022]) and the second semiconductor channel layers (Fig. 3B,215,[0022]); forming a first spacer (Fig. 4C, 247, [0029]) along a sidewall of the dummy gate structure (Fig. 4A,4D, 245,[0026]); forming a first inner spacer (Fig. 8C, 255, [0032]) between the first semiconductor channel layers (Fig. 3B,215,[0022]) and a second inner spacer (Fig. 8C, 255, [0032]) between the second semiconductor channel layers (Fig. 3B,215,[0022]); forming first source/drain structures (Fig. 9A, 260, [0034]) on opposite ends of the first semiconductor channel layers (Fig. 3B,215,[0022]) and second source/drain structures (Fig. 9A, 260, [0034]) on opposite ends of the second semiconductor channel layers (Fig. 3B,215,[0022]); forming a second spacer (Fig. 14C, 280,282, [0041]) alongside the first spacer (247), wherein a combination of the first spacer (247) and the second spacer (280,282) has a first width along a first direction, the first inner spacer (Fig. 8C, 255, [0032]) has a second width along the first direction, and the second inner spacer (Fig. 8C, 255, [0032]) has a third width along the first direction, and wherein the first width is greater than the second width and the third width, and the second width is greater than the third width (Fig. 8C); replacing the dummy gate structure (Fig. 4A,4D, 245,[0026]) with a metal gate structure (Fig. 14A, 14D, 350, [0042]; and forming an isolation structure (Fig. 16C, 262, [0045]) on one end of the metal gate structure (350), the isolation structure (Fig. 16C, 262, [0045]) having a fourth width along a second direction substantially perpendicular to the first direction (Fig. 16C, 262, [0045]), wherein the fourth width is greater than the first width (Fig. 16C, 262, [0045]).
Regarding claim 22, Liaw shows in FIG, 2A-16D, a method wherein the fourth width (Fig. 16C, 262, [0045]) is greater than two times the first width.
Regarding claim 24, Liaw shows in FIG, 2A-16D, a method wherein a first material of the isolation structure (Fig. 16C, 262, [0045]) has a higher dielectric constant than a second material of the first spacer (Fig. 4C, 247, [0029]) and the second spacer (Fig. 14C, 280,282, [0041]) and a third material of the first and second inner spacers (Fig. 8C, 255, [0032]).
Regarding claim 25, Liaw shows in FIG, 2A-16D, a method wherein the third material of the first and second inner spacers (Fig. 8C, 255, [0032]). has a higher dielectric constant than the second material of the first spacer (Fig. 4C, 247, [0029]) and the second spacer (Fig. 14C, 280,282, [0041]).
Regarding claim 27, Liaw shows in FIG, 2A-16D, a method further comprising thinning the first semiconductor channel layers (Fig. 3B,215, [0022]) such that the first semiconductor channel layers (Fig. 3B,215,[0022])are thinner than the second semiconductor channel layers (Fig. 3B,215,[0022])(on other side) along a vertical direction.
Regarding claim 28, Liaw shows in FIG, 2A-16D, a method, comprising: forming first semiconductor channel layers (Fig. 3B,215,[0022]) and second semiconductor channel layers (Fig. 3B,215,[0022]) over a substrate (202); forming a dummy gate structure (Fig. 4A,4D, 245,[0026]) over the first semiconductor channel layers (Fig. 3B,215,[0022]) and the second semiconductor channel layers (Fig. 3B,215,[0022]); forming a first spacer (Fig. 4C, 247, [0029]) along a sidewall of the dummy gate structure (Fig. 4A,4D, 245,[0026]); forming a first inner spacer (Fig. 8C, 255, [0032]) between the first semiconductor channel layers (Fig. 3B,215,[0022]) and a second inner spacer (Fig. 8C, 255, [0032]) between the second semiconductor channel layers (Fig. 3B,215,[0022]); forming first source/drain structures (Fig. 9A, 260, [0034]) on opposite ends of the first semiconductor channel layers (Fig. 3B,215,[0022]) and second source/drain structures (Fig. 9A, 260, [0034]) on opposite ends of the second semiconductor channel layers (Fig. 3B,215,[0022]); forming a second spacer (Fig. 14C, 280,282, [0041]) alongside the first spacer (247), wherein a combination of the first spacer (247) and the second spacer (280,282) has a first width along a first direction, the first inner spacer (Fig. 8C, 255, [0032]) has a second width along the first direction, and the second inner spacer (Fig. 8C, 255, [0032]) has a third width along the first direction, and wherein the first width is greater than the second width and the third width, and the second width is greater than the third width (Fig. 8C); removing the dummy gate structure (Fig. 4A,4D, 245,[0026]) to expose the first semiconductor channel layers (Fig. 3B,215,[0022]) and the second semiconductor channel layers (Fig. 3B,215,[0022]); thinning the first semiconductor channel layers (Fig. 3B,215,[0022]) such that the first semiconductor channel layers (Fig. 3B,215,[0022]) are thinner than the second semiconductor channel layers (Fig. 3B,215,[0022]) (other side) along a vertical direction; and forming a metal gate (Fig. 14C,14D, 350,[0042]) structure over the first semiconductor channel layers (Fig. 3B,215,[0022]) and the second semiconductor channel layers (Fig. 3B,215,[0022]).
Regarding claim 29, Liaw shows in FIG, 2A-16D, a method of claim 28, further comprising narrowing down the second inner spacer (Fig. 8C, 255, [0032]) such that the third width of the second inner spacer (Fig. 8C, 255, [0032]) is less than the second width of the first inner spacer (Fig. 8C, 255, [0032]).
Regarding claim 31, Liaw shows in FIG, 2A-16D, a method of claim 30, wherein an interface between the first inner spacer (Fig. 8C, 255, [0032]) and one of the first source/drain structures (Fig. 9A, 260, [0034]) is substantially aligned with an interface between one of the first semiconductor channel layers (Fig. 3B,215,[0022]) and the one of the first source/drain structures (Fig. 9A, 260, [0034]).
Regarding claim 32, Liaw shows in FIG, 2A-16D, a method, wherein a first material of the first and second inner spacers (Fig. 8C, 255, [0032]) has a higher dielectric constant than a second material of the first and second spacers (Fig. 14C, 280,282, [0041] along the first spacers (247).
As for the different material, It would have been obvious to one having ordinary skill in the art at the time of the invention was made to have a specific material, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use. In re Leshin, 125 USPQ 416. MPEP 2144.07
Regarding claim 33, Liaw shows in FIG, 2A-16D, a method wherein a difference between the first width and the second width (Fig. 8C, 255, [0032]) is less than a difference between the first width and the third width.
Allowable Subject Matter
Claims 18,20,23,26,30,34,35 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Pertinent References
Smith et al., (Smith) US 2023/0071699 discloses a device structure 100A (herein NMOS transistor 100A) that includes a plurality of channel regions 102 (e.g., fin, nanoribbon or nanowire channel regions), each including a respective sidewall 102A and a respective sidewall 102B opposite to the sidewall 102A.
Smith fails to disclose:
A method of forming a dummy gate structure crossing the first stack of the first semiconductor channel layers and the first sacrificial layers and the second stack of the second semiconductor channel layers and the second sacrificial layers; removing the first and second sacrificial layers, such that the first and second semiconductor channel layers are suspended over the substrate; forming a mask over the N-well region of the substrate and covering the second semiconductor channel layers, while leaving the first semiconductor channel layers over the P-well region of the substrate exposed; performing a first etching process to narrow down the first semiconductor channel layers; removing the mask after the first etching process is complete; and forming a common gate structure wrapping around the first and second semiconductor channel layers.
Conclusion
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MARC - ANTHONY ARMAND
Primary Examiner
Art Unit 2813
/MARC-ANTHONY ARMAND/Primary Examiner, Art Unit 2813
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