Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on May 29, 2024 was in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
1. Claims 1-2 and 11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sung et al. (Pub. No.: US 2019/0173048 A1).
Regarding Claim 1, Sung et al. discloses a display device comprising: a substrate comprising a display area in which emission areas are arranged and a non-display area around the display area (Par. 0045-0049; Figs 1-2 – display area DA; non-display area NDA); a circuit layer on the substrate (Par. 0058-0076; Figs 1-2 – circuit layer comprising layers 100, 120, 140, 160, and transistors therein); and an element layer on the circuit layer (Par. 0081-0087; Figs 1-2 – element layer comprising layers 190, 710, 720, 730), wherein the non-display area comprises: a dam area where at least one dam portion surrounding the display area is arranged and spaced apart from the display area (Par. 0062, 0101; Figs 1-2 – dam area comprising dam portion SP (spacer)); and
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a junction area between an edge of the substrate and the dam area (Fig. 2), wherein the circuit layer comprises: a barrier layer on the substrate (Par. 0058-0064; Figs 1-2 – barrier layer 100c); a buffer layer on the barrier layer (Par. 0058-0064; Figs 1-2 – buffer layer 120); and two or more inorganic insulating layers on the buffer layer and containing an inorganic insulating material (Par. 0068-0074; Figs 1-2 – inorganic insulating layers 140 (a silicon oxide (SiOx), a silicon nitride (SiNx), or a silicon oxynitride (SiON)), 160 (a silicon oxide (SiOx), a silicon nitride (SiNx), or a silicon oxynitride (SiON))), the display device further comprising a groove in a part of the junction area, spaced apart from the dam area and the edge of the substrate, and penetrating the barrier layer and the buffer layer (Par. 0062-0064; Figs 1-2 – groove 10a).
Regarding Claim 2, Sung et al., as applied to claim 1, discloses the display device, wherein the two or more inorganic insulating layers extend to a first boundary
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area in contact with the dam area in the junction area (see annotated Fig. 2), a first crack dam is provided by side surfaces of the two or more inorganic insulating layers (see annotated Fig. 2), and the first crack dam is spaced apart from the groove (see annotated Fig. 2).
Regarding Claim 11, Sung et al. discloses a method for manufacturing a display device, comprising: providing a substrate comprising a display area in which emission areas are arranged and a non-display area around the display area Par. 0045-0049; Figs 1-2 – display area DA; non-display area NDA); and
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forming a circuit layer on the substrate (Par. 0058-0076; Figs 1-2 – circuit layer comprising layers 100, 120, 140, 160, and transistors therein), wherein the non-display area comprises: a dam area spaced apart from the display area and surrounding the display area (Par. 0062, 0101; Figs 1-2 – dam area comprising dam portion SP (spacer)); and a junction area between an edge of the substrate and the dam area (Fig. 2), wherein forming the circuit layer comprises: forming a barrier layer by stacking an inorganic insulating material on the substrate (Par. 0058-0 064; Figs 1-2 – barrier layer 100c); forming a buffer layer by stacking an inorganic insulating material on the barrier layer (Par. 0058-0064; Figs 1-2 – buffer layer 120); and forming a groove by partially removing the barrier layer and the buffer layer (Par. 0062-0064; Figs 1-2 – groove 10a), wherein the groove is in a part of the junction area, and is spaced apart from the dam area and the edge of the substrate (Fig. 2).
Allowable Subject Matter
Claims 3-10 and 12-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Cho et al. (Pub. No.: US 2021/0111371 A1) – This prior art teaches a display device comprising: a substrate (100) comprising a display area (DA) in which emission areas are arranged and a non-display area (NDA) around the display area; a circuit layer (comprising layers 111, 109, 107 etc.) on the substrate; and an element layer (comprising 200) on the circuit layer, wherein the non-display area comprises: a dam area (comprising dams 340/350 etc.) where at least one dam portion surrounding the display area is arranged and spaced apart from the display area; and a junction area between an edge of the substrate and the dam area, wherein the circuit layer comprises: a barrier layer on the substrate; a buffer layer (101) on the barrier layer; and two or more inorganic insulating layers (107, 105, 103 etc.) on the buffer layer (101) and containing an inorganic insulating material, the display device further comprising a groove (355) in a part of the junction area, spaced apart from the dam area and the edge of the substrate, and penetrating the barrier layer and the buffer layer (Fig. 2).
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06/19/2026
/SYED I GHEYAS/Primary Examiner, Art Unit 2893
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