DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Satoh (US 2014/0027771).
Regarding claim 1, Satoh discloses a semiconductor package, comprising:
a first die (215A, fig. 2A and paragraph 0016), comprising:
a first through-silicon via (TSV) configured to receive a first address (107, fig. 2A and paragraphs 0019-0039), and
a first logic circuit configured to generate a second address based on the first address (201A, fig. 2A and paragraph 0020); and
a second die (215B, fig. 2A and paragraph 0016), disposed on the first die, comprising:
a second TSV configured to receive the second address (107 of 215B, fig. 2A and paragraphs 0019-0039), and
a second logic circuit connected in series with the first logic circuit and configured to generate a third address based on the second address (201B, fig. 2A and paragraphs 0020-0039).
Regarding claim 2, Satoh further discloses wherein the first logic circuit comprises a counter (paragraphs 0020-0022).
Regarding claim 3, Satoh further discloses wherein the first logic circuit is configured to increment a bit of the first address to generate the second address (paragraphs 0020-0022).
Regarding claim 4, Satoh further discloses wherein the second logic circuit is configured to increment a bit of the second address to generate the third address (paragraphs 0020-0029).
Regarding claim 5, Satoh further discloses wherein the first TSV is configured to receive the first address from a processor (paragraph 0017).
Regarding claim 6, Satoh further discloses wherein the first die further comprises an embedded non-volatile storage structure configured to store the first address (219, fig. 2A and paragraph 0030).
Regarding claim 7, Satoh further discloses wherein the first die further comprises a logic gate electrically coupled to the first TSV and the second TSV (paragraphs 0019-0039).
Regarding claim 8, Satoh further discloses wherein the first die further comprises a logic gate configured to compare the first address to a chip enable signal received by the first die from a processor (paragraphs 0019-0039).
Regarding claim 9, Satoh further discloses wherein the first TSV and second TSV are arranged in a stacked configuration (107, fig. 2A).
Regarding claim 10, Satoh further discloses wherein the first die further comprises:
a third TSV vertically aligned with the first TSV; and
a multiplexer electrically coupling the first TSV to the third TSV (fig. 2A and paragraphs 0019-0039).
Regarding claim 11, Satoh discloses a semiconductor package, comprising:
a first memory die (215A, fig. 2A and paragraphs 0016-0017);
a second memory die (215B, fig. 2A and paragraphs 0016-0017) disposed on the first memory die;
a vertical conductive structure (107, fig. 2A and paragraphs 0018-0039) extending through the first and second memory dies and configured to receive a first memory address;
a first logic circuit configured to generate a second memory address based on the first memory address (201A, fig. 2A and paragraph 0020); and
a second logic circuit configured to compare the first memory address to a control signal value and to determine whether to enable a memory circuit in the first memory die (fig. 2A and paragraphs 0019-0039).
Regarding claim 12, Satoh further discloses another vertical conductive structure extending through the first and second memory dies and configured to receive the control signal value from a processor (107, fig. 2A and paragraphs 0019-0039).
Regarding claim 13, Satoh further discloses wherein the first logic circuit is configured to increment a bit of the first memory address to generate the second memory address (paragraphs 0019-0039).
Regarding claim 14, Satoh further discloses wherein the first logic circuit comprises a counter (paragraphs 0019-0039).
Regarding claim 15, Satoh further discloses wherein the second logic circuit is configured to perform a XNOR operation between the first memory address and the control signal value (paragraphs 0019-0039).
Regarding claim 16, Satoh further discloses wherein the vertical conductive structure comprises a through-silicon via (TSV) structure (107, fig. 2A and paragraphs 0019-0039).
Regarding claim 17, Satoh discloses a method, comprising:
transmitting a first address to a first memory die through a first vertical conductive structure in the first memory die (fig. 2A and paragraphs 0016-0039);
generating, using a counter of the first memory die, a second address based on the first address (fig. 2A and paragraphs 0016-0039);
transmitting the second address to a second memory die through a second vertical conductive structure stacked on the first vertical conductive structure (107, fig. 2A and paragraphs 0016-0039);
comparing the first address to a control signal value (paragraphs 0016-0039); and
determining whether to enable a memory circuit in the first memory die based on the comparing of the first address to the control signal value (paragraphs 0016-0039).
Regarding claim 18, Satoh further discloses wherein generating the second address comprises incrementing a bit of the first memory address (paragraphs 0020-0039).
Regarding claim 19, Satoh further discloses wherein comparing the first address to a control signal value comprises performing a XNOR operation between the first address and the control signal value (paragraphs 0020-0039).
Regarding claim 20, Satoh further discloses receiving the control signal value through a third vertical conductive structure in the first memory die (fig. 2A and paragraphs 0020-0039).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS M MENZ whose telephone number is (571)272-1877. The examiner can normally be reached Monday-Friday 5:30am-2:00pm.
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/DOUGLAS M MENZ/Primary Examiner, Art Unit 2897 3/7/25