DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2 and 5-7, 8, 10-14 are rejected under 35 U.S.C. 103 as being obvious over Chen et al. US 20230062601 A1 (hereinafter referred to as Chen), in view of Hebert US 20200027951 A1 (hereinafter referred to as Hebert)
Regarding claim 1, Chen teaches
A method of fabricating a semiconductor substrate (method of forming “wafer structure W1’”, para. 0042 FIG. 4B), comprising:
forming a first wafer structure (“wafer structure W1” para. 0015 FIG. 1B), comprising:
forming a first dielectric layer (“dielectric layer 102” para. 0015) surrounding a core substrate (“substate 100” para. 0015);
forming a second wafer structure (“wafer structure W2” para. 0033 FIG. 2D), comprising:
forming a buffer layer (“buffer layer 201” para. 0033) over a wafer substrate (“substrate 200” para. 0033);
sequentially forming a capping layer (“semiconductor cap 202” para. 0033) and a protection layer (“sacrificial layer 203” para. 0022) on the buffer layer;
performing a hydrogen implanting process to implant hydrogen ions into the buffer layer to generate a splitting plane (“an implantation process 204 is performed to implant an implantation species through the sacrificial layer 203 and the semiconductor cap 202 into the buffer layer 201, so as to define a cleavage plane CP in the buffer layer 201”, para. 0023 FIG. 2C) in the buffer layer; and FIG. 9.
removing the protection layer to reveal the capping layer; (“after the implantation process is performed, the sacrificial layer 203 is removed”, para. 0030 FIG. 2D)
bonding the second wafer structure to the first wafer structure by performing a bond annealing process to join the capping layer to the barrier oxide layer (“the wafer bonding process is performed by bonding the dielectric layer 205 of the wafer structure W2 to the dielectric layer 102 of the wafer structure W1”, indirectly bonding “dielectric layer 102” and “semiconductor cap 202”, para. 0035 FIG. 3A);
performing a thermal treatment process to the buffer layer of the second wafer structure (an annealing process if performed at about 400° C. to 600° C. for about 5-30 minute to induce splitting, para 0037); and performing a splitting process to split the second wafer structure from the first wafer structure by inducing splitting at the splitting plane (splitting occurs after the anneal process to form “wafer structures W1′ and W2′”, para. 0037-0038).
However, Chen fails to teach forming a second dielectric layer on the first dielectric layer and surrounding the first dielectric layer; and forming a barrier oxide layer surrounding the first dielectric layer, the second dielectric layer and the core substrate;
Nevertheless, Hebert teaches
forming a second dielectric layer (“second oxide layer 423” para. 0067 FIG. 2) on the first dielectric layer (“first oxide layer 421” para. 0067 and surrounding the first dielectric layer; and forming a barrier oxide layer (“third oxide layer 425” para. 0067) surrounding the first dielectric layer, the second dielectric layer and the core substrate.
Chen and Hebert teach the use of wafer surrounded by dielectric oxide. The “engineered layer 420” features a “poly-silicon layer 422” that holds electrostatic charge so that it can be held by an electrostatic chuck (para. 0054 and 0068). The subsequently formed, “second oxide layer 423” and “third oxide layer 425” are configured to flatten the surfaces while the “nitride layer 424” blocks diffusion of contaminants from “substrate 410” (para. 0056-0058 and 0071-0072). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that “wafer structure W1” can be handled by an electrostatic chuck with use of the “poly-silicon layer 422”, can have contaminants from the core “substrate 400” contained by the “nitride layer 424”, and the surfaces flattened by use of the insulating “first and second oxide layers 423 and 425”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method in Chen with the first wafer structure taught in Hebert. The second dielectric layer flattens the surface of a polysilicon layer used for holding electrostatic charge and the barrier oxide flattens the surface of a nitride layer that acts as a diffusion barrier.
Regarding claim 2, Chen, modified by Hebert, teaches the method according to claim 1, wherein the thermal treatment process generates bubbles at the splitting plane of the buffer layer (“hydrogen forms gaseous bubbles inside of buffer layer 201 upon annealing, thereby creating a hydrogen exfoliation layer along the cleavage plane CP in the buffer layer 201” para. 0037), and the splitting process includes mechanically splitting the second wafer structure from the first wafer structure at the splitting plane (“bonded wafer structure BW is split into two separate wafer structures W1′ and W2′ along the cleavage plane CP in the buffer layer 201”, such that the wafers are mechanically split, para. 0038 FIG. 3B).
Regarding claim 4, Chen, modified by Hebert, teaches the method according to claim 1, further comprising a polysilicon layer (“poly-silicon layer 422” para. 0067 FIG. 4)
However, Chen , modified by Hebert, fails to teach forming the polysilicon layer in between the second dielectric layer and the barrier oxide layer.
Nevertheless, the “poly-silicon layer 422” is configured to hold electrostatic charge so that the “engineered layer 420” can be held by an electrostatic chuck. The examiner understands “poly-silicon layer 422” can accomplish this if it is formed directly on the “substrate 410”, “first oxide layer 421”, “second oxide layer 423, “nitride layer 424, or “third oxide layer 425”. As stated in MPEP 2143.E, “a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely that product [was] not of innovation but of ordinary skill and common sense.” Also, the rearrangement of parts is an obvious matter of design choice if the same outcome is expected, see MPEP 2144.VI.C. It is reasonable to expect that forming “poly-silicon layer 422” after the “nitride layer 424” will also allow for “engineered layer 420” to be held by an electrostatic chuck.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method taught between Chen and Hebert by rearranging the order in which the polysilicon layer and the second dielectric layer are formed. Having the polysilicon formed after the second dielectric layer will still enable the first wafer structure to be held electrostatically.
Regarding claim 5, Chen, modified by Hebert, teaches the method according to claim 1, wherein forming the second wafer structure further comprises: after removing the protection layer to reveal the capping layer, forming a bonding layer on the capping layer (“dielectric layer 205 is formed on the semiconductor cap 202” after “sacrificial layer 203” is removed, para. 0030-0031. “Dielectric layer 205” is configured for bonding to “dielectric layer 102”, para. 0031), and wherein bonding the second wafer structure to the first wafer structure includes physically joining the bonding layer to the barrier oxide layer by the bond annealing process (“wafer bonding process is performed by bonding the dielectric layer 205 of the wafer structure W2 to the dielectric layer 102 of the wafer structure W1” para. 0035 FIG. 3A).
Regarding claim 6, Chen, modified by Hebert, teaches the method according to claim 1, wherein the splitting process includes splitting the buffer layer at the splitting plane into a first buffer portion and a second buffer portion, wherein after the splitting process, the first buffer portion is retained on the first wafer structure, and the second buffer portion is removed along with the second wafer structure (“the buffer layer 201 is split into a buffer layer 201a included in the wafer structure W1′ and a buffer layer 201b included in the wafer structure W2′”, para. 0038 FIG. 3B).
Regarding claim 7, Chen, modified by Hebert, teach the method according to claim 6, further comprising performing an acid etching process to remove the first buffer portion to reveal the capping layer (“the buffer layer 201a is removed from the wafer structure W1′ by etching process” using hydrofluoric acid or acetic acid, para. 0043 FIG. 4B).
Regarding claim 8, Chen teaches
A method of fabricating a semiconductor substrate (method of forming “wafer structure W1’”, para. 0042 FIG. 4B), comprising:
forming a first dielectric layer (“dielectric layer 102” para. 0015) and wrapping around an aluminum nitride core substrate (“wafer structure W1” para. 0015 FIG. 1B);
bonding a wafer structure (“wafer structure W2” para. 0033 FIG. 2D) onto the substrate, wherein the wafer structure comprises a splitting plane (“cleavage plane CP” para. 0023); and
performing a thermal treatment process to mechanically split the wafer structure along the splitting plane into a first portion and a second portion (splitting occurs after the anneal process to form “wafer structures W1′ and W2′”, para. 0037-0038), wherein the first portion is joined to the substrate, and the second portion is separated from the first portion and removed from being on the substrate (“buffer layer 201 is split into a buffer layer 201a included in the wafer structure W1′ and a buffer layer 201b included in the wafer structure W2′” para. 0038).
However, Chen fails to teach an aluminum nitride core substrate, a second dielectric layer wrapping around an aluminum nitride core substrate, forming a polysilicon layer on a front-side surface, a backside surface and side surfaces of the second dielectric layer; removing the polysilicon layer from the front-side surface and the side surfaces of the second dielectric layer, so that the polysilicon layer is retained on the backside surface of the second dielectric layer; forming a barrier oxide layer wrapping around the aluminum nitride core substrate, the first dielectric layer, the second dielectric layer and the polysilicon layer; bonding the wafer structure onto the barrier oxide layer; wherein the first portion is joined to the barrier oxide layer, and the second portion is separated from the first portion and removed from being on the barrier oxide layer.
Nevertheless, Hebert teaches
an aluminum nitride core substrate (“insulating substrate 410 includes ceramic aluminum nitride” para. 0066 FIG. 4),
a second dielectric layer wrapping around an aluminum nitride core substrate (“nitride layer 424” para. 0067),
forming a polysilicon layer on a front-side surface, a backside surface and side surfaces of the aluminum nitride core substrate (“poly-silicon layer 422 is first formed to surround the first oxide layer 421” para. 0068);
removing the polysilicon layer from the front-side surface and the side surfaces of the second dielectric layer, so that the polysilicon layer is retained on the backside surface of the second dielectric layer (“the poly-silicon layer 422 is etched back to the surface of the first oxide layer 421 such that the portion of the poly-silicon layer 422 under the insulating substrate 410 is left” para. 0069);
forming a barrier oxide layer wrapping around the aluminum nitride core substrate, the first dielectric layer, the second dielectric layer and the polysilicon layer (“third oxide layer 425” para. 0072).
Chen and Hebert teach the use of wafer surrounded by dielectric oxide. “Insulating substrate 410” is made of aluminum nitride, a ceramic material. The “engineered layer 420” features a “poly-silicon layer 422” that holds electrostatic charge so that it can be held by an electrostatic chuck (para. 0054). The subsequently formed, “second oxide layer 423” and “third oxide layer 425” are configured to flatten the surfaces while the “nitride layer 424” blocks diffusion of contaminants from “substrate 410” (para. 0056-0058). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that “wafer structure W1” can be handled by an electrostatic chuck with use of the “poly-silicon layer 422”, can have contaminants from the core “substrate 400” contained by the “nitride layer 424”, and the surfaces flattened by use of the insulating “first and second oxide layers 423 and 425”. Aluminum nitride is a known material suitable for use as a core substrate.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method in Chen with the first wafer structure taught in Hebert. Aluminum nitride is a known material used as a core substrate. The second dielectric layer is a barrier nitride layer that prevents diffusion and the barrier oxide flattens the surface of a nitride layer that acts as a diffusion barrier. A polysilicon on the bottom surface can hold charge so that an electrostatic chuck can hold the first wafer structure.
Chen, modified by Hebert, further teaches
bonding the wafer structure onto the barrier oxide layer (“wafer structure W1” now bonds directly onto “third oxide layer 425” from Hebert);
wherein the first portion is joined to the barrier oxide layer (“buffer layer 201a” is included in the wafer structure W1′ that now includes “third oxide layer 425”), and the second portion is separated from the first portion and removed from being on the barrier oxide layer (“buffer layer 201b” included in the “wafer structure W2′”).
However, Chen, modified by Hebert fails to expressly teach forming a polysilicon layer on a front-side surface, a backside surface and side surfaces of the second dielectric layer.
Nevertheless, the “poly-silicon layer 422” is configured to hold electrostatic charge so that the “engineered layer 420” can be held by an electrostatic chuck. The examiner understands “poly-silicon layer 422” can accomplish this if it is formed directly on the “substrate 410”, “first oxide layer 421”, “second oxide layer 423, “nitride layer 424, or “third oxide layer 425”. As stated in MPEP 2143.E, “a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely that product [was] not of innovation but of ordinary skill and common sense.” Also, the rearrangement of parts is an obvious matter of design choice if the same outcome is expected, see MPEP 2144.VI.C. It is reasonable to expect that forming “poly-silicon layer 422” after the “nitride layer 424” will also allow for “engineered layer 420” to be held by an electrostatic chuck.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method taught between Chen and Hebert by rearranging the order in which the polysilicon layer and the second dielectric layer are formed. Having the polysilicon formed after the second dielectric layer will still enable the first wafer structure to be held electrostatically.
Regarding claim 10, Chen, modified by Hebert, teach the method according to claim 8, wherein the wafer structure comprising the splitting plane is formed by implanting hydrogen ions into a buffer layer of the wafer structure (“hydrogen ions (H.sup.+) are implanted into the buffer layer 201 to define the cleavage plane CP” Chen para. 0023), and wherein implanting the hydrogen ions generates a gradient layer of hydrogen ions in the buffer layer (hydrogen ions exhibit a Gaussian distribution in the “buffer layer 201” where the ion concentration varies by layer thickness, para. 0025), and a region in the gradient layer having a highest hydrogen ion concentration corresponds to the splitting plane (“the peak of the ion distribution is within the buffer layer 201, and the cleavage plane CP may be defined at the peak location of ion distribution” para. 0026).
Regarding claim 11, Chen, modified by Hebert, teach the method according to claim 10, wherein the buffer layer comprises silicon germanium (“buffer layer 201 is a silicon germanium (SiGe) layer” Chen para. 0018).
Regarding claim 12, Chen, modified by Hebert, teach the method according to claim 10, wherein the first portion of the wafer structure comprises a bonding layer that is bonded to the barrier oxide layer, a capping layer disposed on the bonding layer and a first buffer portion of the buffer layer (after splitting, “wafer structure W1’” now includes “dielectric layer 205”, “semiconductor cap 202” and “buffer layer 201a”, Chen para. 0039 FIG. 3B).
Regarding claim 13, Chen, modified by Hebert, teach the method according to claim 8, wherein bonding the wafer structure onto the barrier oxide layer comprises performing a bond annealing process at a temperature of 300°C to 1000°C (“the wafer bonding process may be performed at about 350° C” para. 0035, where “wafer structure Wi” now includes “third oxide layer 425” from Hebert).
Regarding claim 14, Chen, modified by Hebert, teach the method according to claim 8, wherein the thermal treatment process is performed at a temperature of less than 400°C (“This split may be induced by an annealing process performed at about 400° C. to 600° C”, Chen 1para. 0037. Temperature about, or around, 400° C include temperatures below 400° C).
Claim 3 is rejected under 35 U.S.C. 103 as being obvious over Chen, modified by Hebert, as applied to claim 1 above, in view of Seacrist et al. US 20070117350 A1 (hereinafter referred to as Seacrist)
Chen, modified by Hebert, teach the method according to claim 1 but fail to teach wherein the thermal treatment process is performed at a temperature that is lower than a temperature of the bond anneal process.
Nevertheless, Seacrist teaches in para. 0046 different annealing temperatures and times to induce fracture along a SiGe buffer layer. Also, Seacrist teaches in para. 0047 that a combination of mechanical force and annealing can be combined to induce separation of the bonded wafer structure; any known method of applying force can be applied in addition to an anneal of less than 350°C. These are considered possible known options that achieve the expected result of splitting the buffer layer at the splitting lane. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that there exist a finite number of possible solutions that were obvious to try to induce splitting.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method taught between Chen and Hebert with the possible solutions in Seacrist. Different temperatures are known to achieve a splitting of the buffer layer. As stated in MPEP 2143.E, “a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely that product [was] not of innovation but of ordinary skill and common sense.”
Claim 9 is rejected under 35 U.S.C. 103 as being obvious over Chen, modified by Hebert, as applied to claim 8 above, in view of Odnoblyudnov et al US 20180047558 A1 (hereinafter referred to as Odnoblyudnov), in view of Yokokawa US 20230268222 A1 (hereinafter referred to as Yokokawa).
Chen, modified by Hebert, teaches the method according to claim 8, wherein the first dielectric layer is silicon oxide (“dielectric layer 102 may include an oxide, such as silicon oxide” Chen para. 0014), the second dielectric layer is a nitride (“nitride layer 424”) and the barrier oxide layer is an oxide (“third oxide layer 425).
However, Chen modified by Hebert, fail to teach the second dielectric layer is silicon nitride and the barrier oxide layer is silicon oxide.
Nevertheless, Odnoblyudnov teaches a composite wafer surrounded by a “barrier layer 118” made of silicon nitride that prevents element diffusion (para. 0032). This suggests that silicon nitride is a known diffusion barrier layer. On the other hand, Yokokawa teaches an SOI wafer covered by a “silicon oxide film 50”. Silicon oxide is a well-known dielectric material. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that silicon nitride is a material suitable for use as a diffusion barrier and silicon oxide is suitable for use as an outermost insulating layer.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method taught between Chen and Hebert with the second dielectric layer and the barrier oxide layer taught in Odnoblyudnov and Yokokawa. Silicon nitride is a well-known diffusion barrier and silicon oxide is a well-known insulator, both used in wafer manufacturing.
Claims 15 and 17-20 are rejected under 35 U.S.C. 103 as being obvious over Chen et al. US 20230062601 A1 (hereinafter referred to as Chen), in view of Hebert US 20200027951 A1 (hereinafter referred to as Hebert), in view of Seacrist et al US 20070117350 A1 (hereinafter referred to as Sacrist).
Regrading claim 15, Chen teaches
A method of fabricating a semiconductor substrate, comprising:
forming a first wafer structure (“wafer structure W1” para. 0014 FIG. 1B) having an aluminum nitride core substrate (“substrate 100” para. 0012) and a barrier oxide layer (silicon oxide “dielectric layer 102” para. 0014) wrapping around the aluminum nitride core substrate;
forming a second wafer (“wafer structure W2” para. 0033 FIG. 2D) structure having a buffer layer (“buffer layer 201”, para. 0033) and a bonding layer (“dielectric layer 205” configured for the subsequent wafer bonding process, para. 0031);
performing an implantation process on the buffer layer to generate a splitting plane in the buffer layer (“implantation process 204” defines a “cleavage plane CP”, para. 0023 FIG. 2C-2D);
performing a bond annealing step at a temperature of 300C to 1000C to bond the bonding layer of the second wafer structure to the barrier oxide layer of the first wafer structure (“wafer bonding process is performed to bond the wafer structure W2 to the wafer structure W1” including an anneal process at about 350°C, para. 0035 FIG. 3A); and
and performing a splitting process to split the buffer layer at the splitting plane (“wafer splitting process is performed to split the bonded wafer structure BW along the cleavage plane CP” para. 0037 FIG. 3B).
However, Chen fails to teach the first wafer structure having an aluminum nitride core substrate, performing a thermal treatment process at a temperature lower than the bond annealing step.
Nevertheless, Hebert teaches
the first wafer structure (“engineered layer 420” para. 0065 FIG. 4) having an aluminum nitride core substrate (“insulating substrate 410 includes ceramic aluminum nitride” para. 0066 FIG. 4),
Chen and Hebert teach the use of wafer surrounded by dielectric oxide. “Substrate 100” in Chen is a silicon wafer while “insulating substrate 410” in Hebert is made of aluminum nitride, a ceramic material. Odnoblyudnov et al. US 20180047558 A1 also teaches a “core 110” of aluminum nitride surrounded by oxide and nitride layers (Odnoblyudnov para. 0024 FIG. 1). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that aluminum nitride is a well-known material used as a core substrate.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method in Chen with the aluminum nitride core substrate as taught in Hebert and Odnoblyudnov. Aluminum nitride is a well-known core substrate material used in composite wafer formation.
However, Chen, modified by Hebert and Odnoblyudnov, fails to teach performing a thermal treatment process at a temperature lower than the bond annealing step.
Nevertheless, Seacrist teaches in para. 0046 different annealing temperatures and times to induce fracture along a SiGe buffer layer. Also, Seacrist teaches in para. 0047 that a combination of mechanical force and annealing can be combined to induce separation of the bonded wafer structure; any known method of applying force can be applied in addition to an anneal of less than 350°C. These are considered possible known options that achieve the expected result of splitting the buffer layer at the splitting lane. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that there exist a finite number of possible solutions that were obvious to try to induce splitting.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method taught between Chen and Hebert with the possible solutions in Seacrist. Different temperatures are known to achieve a splitting of the buffer layer. As stated in MPEP 2143.E, “a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely that product [was] not of innovation but of ordinary skill and common sense.”
Regrading claim 17, Chen, modified by Hebert and Seacrist, teaches the method according to claim 15, wherein forming the second wafer structure comprise:
forming the buffer layer on a wafer substrate (“buffer layer 201 is formed on the substrate 200” para. 0018 FIG. 2B);
forming a capping layer (“semiconductor cap 202 is formed on the buffer layer 201” para. 0020 FIG. 2B) and a protection layer (“sacrificial layer 203 is formed on the semiconductor cap 202” para. 0022 FIG. 2C) on the buffer layer;
performing the implantation process to generate the splitting plane in the buffer layer (“an implantation process 204 is performed to implant an implantation species through the sacrificial layer 203 and the semiconductor cap 202 into the buffer layer 201” para. 0023 FIG. 2C);
removing the protection layer to reveal the capping layer (“after the implantation process is performed, the sacrificial layer 203 is removed” para. 0030 FIG. 2D); and
forming the bonding layer on the capping layer (“dielectric layer 205 is formed on the semiconductor cap 202” para. 0031 FIG. 2D).
Regrading claim 18, Chen, modified by Hebert and Seacrist, teaches the method according to claim 17, wherein after the splitting process, the bonding layer, the capping layer and a portion of the buffer layer is retained on the first wafer structure (after splitting, “dielectric layer 205, the semiconductor cap 202 and the buffer layer 201a are transferred from the wafer structure W2 to the wafer structure W1”, para. 0039 FIG 3B).
Regrading claim 19, Chen, modified by Hebert and Seacrist, teaches the method according to claim 18, further comprises performing an etching process to remove the portion of the buffer layer to reveal the capping layer (“the buffer layer 201a is removed from the wafer structure W1′ by etching process” para. 0043), and performing a thinning step on the capping layer (“A planarization process may further be performed to planarize the top surface of the semiconductor cap 202” para. 0043. The examiner understands that by planarizing, part of the top surface is removed and therefore “semiconductor cap 202” is thinned).
Regrading claim 20, Chen, modified by Hebert and Seacrist, teaches the method according to claim 15, wherein the thermal treatment process is performed at the temperature of 400°C or less (as taught in Seacrist para. 0046, the thermal treatment processes can be done at 250°C).
Claim 16 is rejected under 35 U.S.C. 103 as being obvious over Chen, modified by Hebert and Seacrist, as applied to claim 15 above, in view of Odnoblyudnov et al US 20180047558 A1 (hereinafter referred to as Odnoblyudnov), in view of Yokokawa US 20230268222 A1 (hereinafter referred to as Yokokawa).
Chen, modified by Hebert and Seacrist, teaches method according to claim 15 but fails to teach wherein forming the first wafer structure further comprises: forming a silicon oxide layer wrapping around the aluminum nitride core substrate; forming a silicon nitride layer wrapping around the silicon oxide layer; forming a polysilicon layer on the silicon nitride layer over a backside of the aluminum nitride core substrate; and forming the barrier oxide layer wrapping around the polysilicon layer, the silicon nitride layer, the silicon oxide layer and the aluminum nitride core substrate, wherein the barrier oxide layer is in physical contact with the polysilicon layer and the silicon nitride layer.
Nevertheless, Hebert teaches
wherein forming the first wafer structure (“engineered layer 420” para. 0065 FIG. 4) further comprises:
forming an oxide layer wrapping around the aluminum nitride core substrate (“first oxide layer 421” para. 0067 FIG. 4);
forming a nitride layer (“nitride layer 424” para. 0067) wrapping around the silicon oxide layer;
forming a polysilicon layer on the nitride layer over a backside of the aluminum nitride core substrate (“poly-silicon layer 422” para. 0068); and
forming the barrier oxide layer wrapping around the polysilicon layer, the nitride layer, the oxide layer and the aluminum nitride core substrate (“third oxide layer 425” is the outermost layer, para. 0072).
Chen and Hebert teach the use of wafer surrounded by dielectric oxide. “Insulating substrate 410” is made of aluminum nitride, a ceramic material. The “engineered layer 420” features a “poly-silicon layer 422” that holds electrostatic charge so that it can be held by an electrostatic chuck (para. 0054). The subsequently formed, “second oxide layer 423” and “third oxide layer 425” are configured to flatten the surfaces while the “nitride layer 424” blocks diffusion of contaminants from “substrate 410” (para. 0056-0058). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that “wafer structure W1” can be handled by an electrostatic chuck with use of the “poly-silicon layer 422”, can have contaminants from the core “substrate 400” contained by the “nitride layer 424”, and the surfaces flattened by use of the insulating “first and second oxide layers 423 and 425”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method in Chen with the first wafer structure taught in Hebert. The second dielectric layer is a barrier nitride layer that prevents diffusion and the barrier oxide flattens the surface of a nitride layer that acts as a diffusion barrier. A polysilicon on the bottom surface can hold charge so that an electrostatic chuck can hold the first wafer structure.
However, Chen, modified by Hebert, fails to teach a silicon oxide layer wrapping around the aluminum nitride core substrate, a silicon nitride layer wrapping around the silicon oxide layer, wherein the barrier oxide layer is in physical contact with the polysilicon layer and the silicon nitride layer.
Nevertheless, Odnoblyudnov teaches a composite wafer surrounded by a “barrier layer 118” made of silicon nitride that prevents element diffusion (para. 0032). This suggests that silicon nitride is a known diffusion barrier layer. On the other hand, Yokokawa teaches an SOI wafer covered by a “silicon oxide film 50”. Silicon oxide is a well-known dielectric material. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that silicon nitride is a material suitable for use as a diffusion barrier and silicon oxide is suitable for use as an insulating layer.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method taught between Chen and Hebert with the silicon oxide layer and the silicon nitride layer taught in Odnoblyudnov and Yokokawa. Silicon nitride is a well-known diffusion barrier and silicon oxide is a well-known insulator, both used in wafer manufacturing.
However, Chen, modified by Hebert, Odnoblyudnov, and Yokokawa, fails to teach wherein the barrier oxide layer is in physical contact with the polysilicon layer and the silicon nitride layer.
Nevertheless, the “poly-silicon layer 422” is configured to hold electrostatic charge so that the “engineered layer 420” can be held by an electrostatic chuck. The examiner understands “poly-silicon layer 422” can accomplish this if it is formed directly on the “substrate 410”, “first oxide layer 421”, “second oxide layer 423, “nitride layer 424, or “third oxide layer 425”. As stated in MPEP 2143.E, “a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely that product [was] not of innovation but of ordinary skill and common sense.” Also, the rearrangement of parts is an obvious matter of design choice if the same outcome is expected, see MPEP 2144.VI.C. It is reasonable to expect that forming “poly-silicon layer 422” after the “nitride layer 424” will also allow for “engineered layer 420” to be held by an electrostatic chuck.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method taught between Chen, Hebert, Odnoblyudnov, and Yokokawa by rearranging the order in which the polysilicon layer and the second dielectric layer are formed. Having the polysilicon formed after the second dielectric layer so that it contacts the barrier oxide and the silicon nitride layer will still enable the first wafer structure to be held electrostatically.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC MULERO FLORES whose telephone number is (571)270-0070. The examiner can normally be reached Mon-Fri 8am-5pm (typically).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571)272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ERIC MANUEL MULERO FLORES/ Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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