DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3, 6-8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Coursey (US Pub no. 2014/0183443 A1).
Regarding claim 1, Coursey et al discloses A method of fabricating a semiconductor structure(fig. 3a-3f), comprising: providing a first wafer structure, wherein the first wafer structure comprises: a ceramic substrate(320)[0016], including a surface and at least one hole(326) on the surface(324) [0017]; and a first bonding layer(318) [0018], disposed on the surface(324) of the ceramic substrate(320), and a portion of the first bonding layer fills the at least one hole(326)[0018]; providing a second wafer structure(308)[0011], wherein the second wafer structure (308)comprises: a semiconductor layer(316) comprising a surface(312)[0011][0015]; and a second bonding layer(305), disposed on a surface of the semiconductor layer(316) [0015]; and bonding the first wafer structure(320) and the second wafer structure (308)so that the first bonding layer (318)and the second bonding layer(305)
enclose at least one cavity(326)[0020], wherein the at least one cavity (326)overlaps the at least one hole(326)[0020] fig. 3E.
Regarding claim 3, Coursey et al discloses wherein the step of forming the first wafer structure comprises: providing the ceramic substrate(320); and depositing the first bonding layer(318) on the surface of the ceramic substrate(320)[0016][0018].
Regarding claim 6, Coursey et al discloses wherein: before bonding the first wafer structure(320) and the second wafer structure(308), the second wafer structure further comprises a carrier layer(308), and the carrier layer (309)and the semiconductor layer(316) form a monolithic structure[0015][0021]; before bonding the first wafer structure (320)and the second wafer structure(308), further comprising performing a doping process to form a doped layer (314)between the carrier layer(309) and the semiconductor layer(316)[0015]; and after bonding the first wafer structure(320) and the second wafer structure(308), further comprising separating the carrier layer (309)and the semiconductor layer (316)along a doped plane constituted by the doped layer (314)to thereby expose the doped layer(314)[0021].
Regarding claim 7, wherein after exposing the doped surface, the semiconductor layer(316) extends above the at least one cavity(326)[0022] fig. 3f.
Regarding claim 8, wherein after bonding the first wafer structure(320) and the second
wafer structure(308), the second bonding layer (305)covers the surface of the ceramic substrate (320)and extends across the at least one cavity(326) fig. 3f
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Coursey (US Pub no. 2014/0183443 A1) in view of Nishimura (US Pub no. 2022/0314357 A1-cited in IDS).
Regarding claim 2, Coursey et al discloses all the claim limitations of claim 1 and further teaches wherein: at least one of the depth and the width of the at least one hole
is in a range [0017]; and materials of the first bonding layer(318) and the second bonding layer(305) comprises oxides[0015][0020] but fails to teach comprise silicon-containing oxides; and at least one of the depth and the width of the at least one hole is in a range of 10 µm to 30 um. However, it would have been obvious to one of ordinary skill in the art before the effective filing date to achieve at least one hole is in a range of 10 µm to 30 um by optimizing manufacturing processes through routine experimentation. In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990)
Nishimura et al discloses a method of manufacturing a composite substrate wherein materials of a first bonding layer (40a) and a second bonding layer(22) comprise silicon-containing oxides[0081]. Since silicon oxide materials is one of finite solution to prevent flaking of a composite substrate, it would have been obvious to one of ordinary skill in the art to try in Coursey et al. since a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely the product not of innovation but of ordinary skill and common sense (KSR International Co. V. Teleflex Inc., 82 USPQ2d 1385 (U.S. 2007))
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Coursey (US Pub no. 2014/0183443 A1) in view of Odnoblyudov (US Pub no. 2017/0309676 A1).
Regarding claim 4, Coursey et al discloses all the claim limitations of claim 3 and further teaches wherein the step of depositing the first bonding layer (318)on the surface of the ceramic substrate(320) comprises: depositing a first filling layer in the at least one hole(326)[0019](Coursey teaches defects in front surface 328 and defect mitigation material 318 having an intra-granular roughness with larger defects 326 interspersed throughout)but fails to teach surface of the ceramic substrate comprises: depositing a first filling layer in the at least one hole; and depositing a second filling layer on the first filling layer and in the at least one hole, wherein a surface of the second filling layer comprises at least one recess.
However, Odnoblyudov et al discloses using engineered layers 114 and 115 over ceramic wafer (112)[0024-0025]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the inventio to modify Coursey et al such that depositing a second filling layer on the first filling layer and in the at least one hole, wherein a surface of the second filling layer comprises at least one recess results to provide defectivity management.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Coursey (US Pub no. 2014/0183443 A1) in view of Guo (US Pub no. 2019/0051524 A1).
Regarding claim 5, Coursey et al discloses all the claim limitations of claim 1 but fails to teach wherein before bonding the first wafer structure and the second wafer structure, the method further comprises: performing a planarization process to planarize a surface of the first bonding layer and a surface of the second bonding layer, respectively; and after performing the planarization process, performing a plasma treatment process on the surface of the first bonding layer and the surface of the second bonding layer.
However, Guo et al discloses a wafer bonding method wherein before bonding the first wafer structure and the second wafer structure, the method further comprises: performing a planarization process to planarize a surface of the first bonding layer and a surface of the second bonding layer, respectively[0067]; and
after performing the planarization process, performing a plasma treatment process on the surface of the first bonding layer and the surface of the second bonding layer[0067]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the method of Coursey et al with the teachings of Guo et al to enhance wafer bonding.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Coursey (US Pub no. 2014/0183443 A1) in view Tang (US Pub no. 2011/0215407 A1).
Regarding claim 9, Coursey et al discloses all the claim limitations of claim 1 but fails to teach wherein the semiconductor layer comprises the surface and a further surface opposite to the surface, and the method further comprises planarizing the further surface of the semiconductor layer after bonding the first bonding layer and the second bonding layer.
However, Tang et al discloses method further comprises planarizing the further surface of the semiconductor layer (302)after bonding the first and second wafer(102/202)[0036]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the invention of Coursey et al with the teachings of Tang et al such that the method further comprises planarizing the further surface of the semiconductor layer after bonding the first bonding layer and the second bonding layer results to facilitate further processing of the structure.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Coursey (US Pub no. 2014/0183443 A1) in view Tang (US Pub no. 2011/0215407 A1) as applied to claim 9 and further in view of Odnoblyudov (US Pub no. 2017/0309676 A1).
Regarding claim 10, Coursey et al as modified by Tang et al discloses all the claim limitations of claim 9 and further teaches wherein after planarizing the other surface of the semiconductor layer(Tang et al [0036]), the method further comprises forming a device layer on the further surface(Coursey et al (330) but fails to teach wherein the device layer comprises at least one electrode, an interconnection structure, and at least one dielectric layer.
However, Odnoblyudov et al discloses the device layer comprises at least one
electrode(160), an interconnection structure(162), and at least one dielectric
layer(163) [0042]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to further modify Coursey et al & Tang et al to provide an integrated device.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LATANYA N CRAWFORD EASON whose telephone number is (571)270-3208. The examiner can normally be reached Monday-Friday 8:30 AM-4:30 PM.
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/LATANYA N CRAWFORD EASON/Primary Examiner, Art Unit 2813
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