DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to the communications dated 05/29/2024.
Claims 1-16 are pending in this application.
Acknowledges
2. Receipt is acknowledged of the following items from the Applicant.
Information Disclosure Statement (IDS) filed on 05/29/2024. The references cited on the PTOL 1449 form have been considered.
Applicant is requested to cite any relevant prior art if being aware on form PTO-1449 in accordance with the guidelines set for in M.P.E.P. 609.
Specification
3. The specification has been checked to the extent necessary to determine the presence of possible minor errors. However, the applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
4. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
5. Claims 1-2, 6-9, and 13-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hai et al. (US 2022/0399421)
Regarding claim 1, Hai discloses a semiconductor structure, comprising:
a substrate 1 (see fig. 11);
a device structure layer 5-9, 17a, disposed on the substrate 1;
a dielectric layer 411, disposed on the device structure layer 5-9;
an organic light-emitting diode (OLED) device 301-303 (para. 0098), disposed on the dielectric layer 411;
a light shielding layer 401 or 403 (paras. 0122, 0157, 0158), disposed between the dielectric layer 411 and the device structure layer 5-9, or disposed between the dielectric layer 411 and the OLED device 301-303, or disposed between the dielectric layer 411 and the device structure layer 5-9 and between the dielectric layer 411 and the OLED device 301-303; and
a conductive via (vertically connected to connection electrode 10 at its bottom and to OLED first electrode 301 at its top), disposed in the dielectric layer 410 and the light shielding layer 401, 403, and electrically connected to the OLED device 301-303 and the device structure layer 17a.
Regarding claim 2, Hai discloses the semiconductor structure of claim 1, wherein the light shielding layer is 401, 403 in contact with the conductive via. See fig. 11.
Note: claims 2 and 3 are considered to be obvious variance from one and another. Should Applicant believes that these claimed features are patentably distinct features, Applicant is required to select a single feature for further prosecution.
Regarding claim 6, Hai discloses the semiconductor structure of claim 1, wherein the conductive via is connected to a bottom electrode 301 of the OLED device. See fig. 11.
Regarding claim 7, Hai discloses the semiconductor structure of claim 1, wherein the conductive via is connected to a pad 10 or 15a in the device structure layer 17a. See fig. 11.
Regarding claim 8, Hai discloses a manufacturing method of a semiconductor structure, comprising:
providing a substrate 1 (see fig. 11);
forming a device structure layer 5-9, 17a on the substrate 1;
forming a dielectric layer 411 on the device structure layer 5-9, 171;
forming an organic light-emitting diode (OLED) device 301-303 (para. 0098) on the dielectric layer 411;
forming a light shielding layer 401 or 403 (paras. 0122, 0157, 0158), wherein the light shielding layer 401, 403 is formed between the dielectric layer 411 and the device structure layer 5-9, 171, or between the dielectric layer and the OLED device 401-043, or between the dielectric layer 411 and the device structure layer 5-9, 171 and between the device structure layer and the OLED device; and
forming a conductive via (vertically connected to connection electrode 10 at its bottom and to OLED first electrode 301 at its top), in the dielectric layer 410 and the light shielding layer 401, 403, wherein the conductive via is electrically connected to the OLED device 401-403 and the device structure layer.
Regarding claims 9, 13, 14, Hai discloses the manufacturing methods comprising all claimed limitations. See the rejections of claims 2, 6, 7, respectively.
Regarding claim 15, Hai discloses the manufacturing method of claim 8, wherein the light shielding layer 401 is formed after forming the device structure layer 1-9 and before forming the dielectric layer 411. See fig. 11.
Regarding claim 16, Hai discloses the manufacturing method of claim 8, wherein the conductive via is formed after forming the dielectric layer 411 and before forming the OLED device 301-303, and the light shielding layer 403 is formed after forming the dielectric layer 411 and before forming the conductive via. See fig. 11.
6. Claims 1, 3, 6-8, 10, and 13-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yu et al. (US 2021/0217833)
Regarding claim 1, Yu discloses a semiconductor structure, comprising:
a substrate 10 (see fig. 5);
a device structure layer (comprising transistor T1 shown in top drawing in fig. 5), disposed on the substrate 10;
a dielectric layer 62 or 63, disposed on the device structure layer T1;
an organic light-emitting diode (OLED) device 31-33 (paras. 0030-0033), disposed on the dielectric layer 62, 63;
a light shielding layer 50, disposed between the dielectric layer 63 and the device structure layer T1, or disposed between the dielectric layer 62 and the OLED device 31-33, or disposed between the dielectric layer 63 and the device structure layer T1 and between the dielectric layer 62 and the OLED device 31-33; and
a conductive via (connecting between drain electrode d1 to anode 31), disposed in the dielectric layer 62, 63 and the light shielding layer 50, and electrically connected to the OLED device and the device structure layer.
Regarding claim 3, Yu discloses the semiconductor structure of claim 1, wherein the light shielding layer 50 is not in contact with the conductive via. See fig. 5.
Regarding claim 6, Yu discloses the semiconductor structure of claim 1, wherein the conductive via is connected to a bottom electrode 31 of the OLED device. See fig. 5.
Regarding claim 7, Yu discloses the semiconductor structure of claim 1, wherein the conductive via is connected to a pad d1 in the device structure layer. See fig. 5.
Regarding claim 8, Yu discloses a manufacturing method of a semiconductor structure, comprising:
providing a substrate 10 (see fig. 5);
forming a device structure layer (comprising transistor T1 shown in top drawing in fig. 5) on the substrate 10;
forming a dielectric layer 62 or 63 on the device structure layer T1;
forming an organic light-emitting diode (OLED) device 31-33 (paras. 0030-0033) on the dielectric layer 62, 63;
forming a light shielding layer 50, wherein the light shielding layer 50 is formed between the dielectric layer 63 and the device structure layer T1, or between the dielectric layer 62 and the OLED device 31-33, or between the dielectric layer 63 and the device structure layer T1 and between the device structure layer T1 and the OLED device 31-33; and
forming a conductive via (connecting between drain electrode d1 to anode 31) in the dielectric layer 62, 63 and the light shielding layer 50, wherein the conductive via is electrically connected to the OLED device and the device structure layer.
Regarding claim 10, Yu discloses the manufacturing method of claim 8, wherein the light shielding layer 50 is not in contact with the conductive via. See fig. 5.
Regarding claim 13, Yu discloses the manufacturing method of claim 8, wherein the conductive via is connected to a bottom electrode 31 of the OLED device. See fig. 5.
Regarding claim 14, Yu discloses the manufacturing method of claim 8, wherein the conductive via is connected to a pad d1in the device structure layer. See fig. 5.
Regarding claim 15, Yu discloses the manufacturing method of claim 8, wherein the light shielding layer 50 is formed after forming the device structure layer T1 and before forming the dielectric layer 63. See fig. 5.
Regarding claim 16, Yu discloses the manufacturing method of claim 8, wherein the conductive via is formed after forming the dielectric layer 62 and before forming the OLED device 31-33, and the light shielding layer 50 is formed after forming the dielectric layer 62 and before forming the conductive via. See fig. 5.
7. Claims 1, 4-5, 8, and 11-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jung et al. (US 10,991,786)
Regarding claim 1, Jung discloses a semiconductor structure, comprising:
a substrate 110 (see fig. 1);
a device structure layer (comprising active elements having contact electrodes 120; see col. 6, lines 4-36), disposed on the substrate 110;
a dielectric layer 131 or 132, disposed on the device structure layer;
an organic light-emitting diode (OLED) device (comprising anode 150; see col. 6, lines 4-16, and lines 45-64), disposed on the dielectric layer 131/132;
a light shielding layer 139, disposed between the dielectric layer 132 and the device structure layer, or disposed between the dielectric layer 131 and the OLED device, or disposed between the dielectric layer 132 and the device structure layer and between the dielectric layer 131 and the OLED device; and
a conductive via 140, disposed in the dielectric layer 131/132 and the light shielding layer 139, and electrically connected to the OLED device and the device structure layer.
Regarding claim 4, Jung discloses the semiconductor structure of claim 1, wherein a material of the light shielding layer 139 comprises a nitrogen-containing compound or amorphous silicon. See col. 7, lines 37-58.
Regarding claim 5, Jung discloses the semiconductor structure of claim 4, wherein the nitrogen-containing compound comprises SiN, SiON or SiCN. See col. 7, lines 37-58.
Regarding claim 8, Jung discloses a manufacturing method of a semiconductor structure, comprising:
providing a substrate 110 (see fig. 1);
forming a device structure layer (comprising active elements having contact electrodes 120; see col. 6, lines 4-36) on the substrate 110;
forming a dielectric layer 131 or 132 on the device structure layer;
forming an organic light-emitting diode (OLED) device (comprising anode 150; see col. 6, lines 4-16, and lines 45-64) on the dielectric layer 131/132;
forming a light shielding layer 139, wherein the light shielding layer is formed between the dielectric layer 132 and the device structure layer, or between the dielectric layer 131 and the OLED device, or between the dielectric layer 132 and the device structure layer and between the device structure layer and the OLED device; and
forming a conductive via 140 in the dielectric layer 131/132 and the light shielding layer 139, wherein the conductive via 140 is electrically connected to the OLED device and the device structure layer.
Regarding claims 11-12, Jung discloses the manufacturing methods comprising all claimed limitations. See the rejections of claims 4-5, respectively.
Conclusion
8. A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the day of this letter. Failure to respond within the period for response will cause the application to become abandoned (see M.P.E.P 710.02(b)).
A shortened time for reply may be extended up to the maximum six-month period (35 U.S.C. 133). An extension of time fee is normally required to be paid if the reply period is extended. The amount of the fee is dependent upon the length of the extension. Extensions of time are generally not available after an application has been allowed.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Dao H. Nguyen whose telephone number is (571)272-1791. The examiner can normally be reached on Monday-Friday, 9:00 AM – 5:00 PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke, can be reached on (571)272-1657. The fax numbers for all communication(s) is 571-273-8300.
Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is (571)272-1633.
/DAO H NGUYEN/Primary Examiner, Art Unit 2818 June 17, 2026
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