DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-14 in the reply filed on 08/06/2026 is acknowledged.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7 & 9-12 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US Pub. 2017/0263518) in view of Denham (US Pub. 2006/0224912) and Dabral et al. (US Pub. 2024/0105626) .
Regarding claim 1, Yu teaches a semiconductor device structure, comprising:
an interposer, comprising:
a first semiconductor die 100B (Fig. 19); and
a second semiconductor die 100C (Fig. 19); and
a first electronic component 66B disposed on the interposer and in communication with the first semiconductor die 100A and the second semiconductor die 100B (Fig. 19);
PNG
media_image1.png
814
994
media_image1.png
Greyscale
Yu is silent on (a) wherein the first semiconductor die 100A comprises a first cache memory and a first memory control circuit and the second semiconductor die 100B comprising a second cache memory and a second memory control circuit; and (b) wherein the first semiconductor die comprises at least one first air gap structure.
Denham teaches (a) a first semiconductor die 102 comprising a first cache memory and a first memory control circuit and a second semiconductor die 104 comprising a second cache memory and a second memory control circuit (Fig. 1 and Para 0021]). This presents the advantages of storing data and controlling the data transfer/flow between the various components of the semiconductor device and/with external devices. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Yu with the cache memory and memory control circuits, as taught by Denham, so as to store and control transfer of data.
Debral teaches (b) in Fig. 2 and Fig. 9 an interposer comprising at least one air gap structure 185. This has the advantages of providing a substantially low dielectric constant to reduce parasitic capacitance between the closely spaced conductive layers. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Yu & Denham with the airgap structure, as taught by Debral, so as to obtain a semiconductor device with reduced parasitic capacitance.
Regarding claim 2, the combination of Yu, Denham and Debral teaches the semiconductor device structure of claim 1, further comprising: a redistribution structure disposed between the interposer and the first electronic component 66B (see Fig. 19 above).
Regarding claim 3, the combination of Yu, Denham and Debral teaches the semiconductor device structure of claim 2, further comprising: a second electronic component (66A or 66C) disposed on the interposer, wherein the second electronic component is in communication with the first electronic component via the redistribution structure (see Fig. 19 above).
Regarding claim 4, the combination of Yu, Denham and Debral teaches the semiconductor device structure of claim 3, wherein the second electronic component comprises a dynamic random-access memory (DRAM) (Yu’s Fig. 19).
Regarding claim 5, the combination of Yu, Denham and Debral teaches the semiconductor device structure of claim 4, wherein the first cache memory comprises a static random-access memory (SRAM) (Yu’s Fig. 19).
Regarding claim 6, the combination of Yu, Denham and Debral teaches the semiconductor device structure of claim 5, wherein the second cache memory comprises an SRAM (Yu’s Fig. 19).
With respect claims 4-6, the limitations (DRAM and SRAM) are recitation of the intended use of the claimed invention, and such use must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim.
Regarding claim 7, the combination of Yu, Denham and Debral teaches the semiconductor device structure of claim 1, wherein a distance from the first cache memory to the second cache memory is less than a distance from the first memory control circuit to the second cache memory (it is understood that the two cache memories can be closer to one another due to their storage characteristics).
Regarding claim 8, the combination of Yu, Denham and Debral teaches the semiconductor device structure of claim 1, wherein the first cache memory is closer to the second memory control circuit than to the second cache memory (it is understood that positioning the first cache memory closer to the second memory control circuit would have required routine and ordinary skill in the art to obtain a slightly different arrangement of components within the semiconductor device).
Regarding claim 9, the combination of Yu, Denham and Debral teaches the semiconductor device structure of claim 1, further comprising: an encapsulant 144 encapsulating the first semiconductor die and the second semiconductor die (Yu’s Fig. 19).
Regarding claim 10, the combination of Yu, Denham and Debral teaches the semiconductor device structure of claim 1, wherein the first semiconductor die 100B has a first surface and a second surface opposite to the first surface and facing the first electronic component 66B, wherein the first cache memory is disposed adjacent to the second surface of the first semiconductor die (Yu’s Fig. 19 and Denham’s Fig. 1 and Para 0021]).
Regarding claim 11, the combination of Yu, Denham and Debral teaches the semiconductor device structure of claim 10, wherein the first semiconductor die comprises at least one first through via (136A-136B) extending from the first surface of the first semiconductor die (Yu’s Fig. 19).
Regarding claim 12, the combination of Yu, Denham and Debral teaches the semiconductor device structure of claim 1, wherein the first electronic component 66B vertically overlaps the first cache memory and the second cache memory ((Yu’s Fig. 19 and Denham’s Fig. 1 & Para [0021]).
Regarding claim 13, the combination of Yu, Denham and Debral teaches the semiconductor device structure of claim 11, wherein the first air gap structure is disposed between two adjacent first through vias (Debral’s Fig. 2 & 9 and associated texts).
Allowable Subject Matter
Claim 14 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIMOR KARIMY whose telephone number is (571)272-9006. The examiner can normally be reached Monday - Friday: 8:30 AM -5:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TIMOR KARIMY/Primary Examiner, Art Unit 2818
Prosecution Insights