DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) filed on 6/23/20265 is/are in compliance with provisions of 37 CFR 1.97. Accordingly, the information disclosure is being considered by the Examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dain Lee et al, (hereinafter LEE), US 20220093387 A1, in view of I-Chen Yang et al, (hereinafter YANG), TW 1397181 B.
Regarding Claim 1, LEE teaches a semiconductor device (Fig. 2A, [0028]), comprising:
a substrate (Fig. 2A, 10);
a plurality of recesses recessed (Fig. 2A, R, contact recess) from a top surface (annotated Figure 2A) of the substrate (Fig. 2A. 10) defining a channel region (Figs. 2A/2C, AR, active regions, [0029]) between the plurality of recesses (Fig. 2A, R, contact recess) and adjacent to the top surface (annotated Figure 2A) of the substrate (Fig. 2A, 10);
a gate structure (annotated Figure 2A) positioned on the channel region (Figs. 2A/2C, AR, active regions, [0029]); and
a plurality of impurity regions (Fig. 2A, 1a/1b, first/second impurity region) comprising:
a plurality of lightly doped portions positioned within the substrate ([0028]) and separated from each other (annotated Figure 2A) with the channel region in between (Figs. 2A/2C, AR, active regions, [0029]); and
a plurality of bulk doped portions ([0030]) positioned within the substrate (Fig. 2A, 10), and respectively and correspondingly connected to the plurality of lightly doped portions ([0028]);
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Though LEE teaches thickness of various layers, such as spacer layers, seed layer, and capping layer, LEE does not explicitly disclose a semiconductor device, wherein a ratio of a thickness of the gate structure to a maximal depth between the top surface of the substrate and a top surface of the plurality of lightly doped portions is between about 7.00 and about 3.60.
YANG teaches a semiconductor device (Fig. 2, [0045]), wherein a ratio of a thickness of the gate structure (Fig. 2, 204b, thickness of the gate dielectric layer, for example, about 20 to 35, [0037]) to a maximal depth (Fig. 2, D1, height difference between the first surface, 201a, and the second surface, 201b is between 250 and 600, [0035]) between the top surface of the substrate (Fig. 2, 200) and a top surface of the plurality of lightly doped portions (Fig. 2, 208), is between about 7.00 and about 3.60 (Based on above data range, simple ratio calculation results 250/35 = 7.14).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified LEE to incorporate the teachings of YANG, such that a semiconductor device, wherein a ratio of a thickness of the gate structure to a maximal depth between the top surface of the substrate and a top surface of the plurality of lightly doped portions is between about 7.00 and about 3.60, so that it enables to control the device characteristics such as leakage current, hot carrier effect or short channel effect (SCE) in order to improve the speed and performance of components with the reduction in size of the entire circuit components (YANG, [0002]).
The combination of LEE and YANG does not appear to expressly state, a semiconductor device, wherein a ratio of a thickness of the gate structure to a maximal depth between the top surface of the substrate and a top surface of the plurality of lightly doped portions is between about 7.00 and about 3.60; however, where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. See MPEP §2144.05 II A; see also In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
In the case at hand, YANG teaches the general conditions of claim 1. Specifically, the field indicated by YANG regarding the dimensions such as a ratio of a thickness of the gate structure to a maximal depth between the top surface of the substrate and a top surface of the plurality of lightly doped portions is the variable describe by the range is "result-effective," i.e. the prior art discloses/teaches that the range/variable in question is one that, which changed, results in a demonstrable/desired effect. For instance, a ratio of a thickness of the gate structure to a maximal depth between the top surface of the substrate and a top surface of the plurality of lightly doped portions can be changed to the effect of having a desirable device characteristics, to control the leakage current. Therefore, one having ordinary skill in the at the time the application at hand would find it obvious to discover the optimum or workable ranges, for example, a ratio of a thickness of the gate structure to a maximal depth between the top surface of the substrate and a top surface of the plurality of lightly doped portions is between about 7.00 and about 3.60 using only routine skill in the art.
Regarding Claim 2, LEE as modified by YANG teaches the semiconductor device of claim 1.
LEE further teaches the semiconductor device (Fig. 2A, [0028]), wherein the gate structure (annotated Figure 2A above) comprises:
a gate dielectric layer (Figs. 2B/2C, 21, gate insulating film) positioned on the substrate (Fig. 2C, 10) and between the plurality of recesses (Fig. 2A, R, contact recess);
a gate bottom conductive layer (Figs. 2B/2C, 23 (WL), word lines include a conductive material, [0031]) positioned on the gate dielectric layer (Figs. 2B/2C, 21, gate insulating film);
a gate top conductive layer (Figs. 2B/2C, upper surface of the word lines, 23 (WL), [0031]) positioned on the gate bottom conductive layer (Figs. 2B/2C, 23 (WL), word lines include a conductive material, [0031]); and
a gate capping layer (Figs. 2B/2C, 25) positioned on the gate top conductive layer (Figs. 2B/2C, 23 (WL), word lines include a conductive material, [0031]).
Regarding Claim 3, LEE as modified by YANG teaches the semiconductor device of claim 2.
LEE further teaches the semiconductor device (Fig. 2A, [0028]), wherein a width (annotated Figure 2B) of the gate dielectric layer (Figs. 2B/2C, 21, gate insulating film) is greater than a width (annotated Figure 2B) of the gate bottom conductive layer (Figs. 2B/2C, 23 (WL), word lines include a conductive material, [0031]).
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Regarding Claim 4, LEE as modified by YANG teaches the semiconductor device of claim 2.
LEE further teaches the semiconductor device (Fig. 2A, [0028]), further comprising an inner spacer layer (Fig. 2A, 41) positioned on the substrate (Fig. 2A, 10) and covering the gate structure (annotated Figure 2A above).
Regarding Claim 5, LEE as modified by YANG teaches the semiconductor device of claim 4.
LEE further teaches the semiconductor device (Fig. 2A, [0028]), further comprising a middle spacer layer (Fig. 2A, 47, protective spacer) positioned on the plurality of lightly doped portions ([0028]) and covering the inner spacer layer (Fig. 2A, 41).
Regarding Claim 6, LEE as modified by YANG teaches the semiconductor device of claim 5.
LEE further teaches the semiconductor device (Fig. 2A, [0028]), further comprising an outer space layer (Fig. 2A, 49/OS, main spacer/outer spacer) positioned on the plurality of bulk doped portions ([0030]) and covering the middle spacer layer (Fig. 2A, 47, protective spacer).
Regarding Claim 7, LEE as modified by YANG teaches the semiconductor device of claim 6.
LEE further teaches the semiconductor device (Fig. 2A, [0028]), further comprising a first insulating layer (Fig. 2E, 51, capping patter may include at least one of SiN and SiBN, [0079]) positioned on the outer space layer (Fig. 2A, 49/OS, main spacer/outer spacer).
Regarding Claim 8, LEE as modified by YANG teaches the semiconductor device of claim 7.
LEE further teaches the semiconductor device (Fig. 2A, [0028]), wherein the inner spacer layer (Fig. 2A, 41) and the outer space layer (Fig. 2A, 49/OS, main spacer/outer spacer) comprise the same material (silicon nitride, [0067], [0112]).
Regarding Claim 9, LEE as modified by YANG teaches the semiconductor device of claim 2.
LEE further teaches the semiconductor device (Fig. 2A, [0028]), further comprising a plurality of contacts (Fig. 2A, BC, storage node contacts, [0036]) positioned on the plurality of bulk doped portions ([0030]).
Regarding Claim 10, LEE as modified by YANG teaches the semiconductor device of claim 2.
YANG further teaches the semiconductor device (Fig. 2, [0045]), wherein a ratio of the thickness of the gate structure (Fig. 2, 204a, the length of the gate structure 204a can be as small as 90 nm, [0037]) to a thickness of the plurality of lightly doped portions (Fig. 2, 208, D2, horizontal distance between the first surface, 201a and the second surface, 201b is between 250 and 350) is between about 3.50 and about 2.20 (Based on above data range, simple ratio calculation results 250/90 = 2.77 or 35/90 = 3.88).
The combination of LEE and YANG does not appear to expressly state, a semiconductor device, a ratio of the thickness of the gate structure to a thickness of the plurality of lightly doped portions is between about 3.50 and about 2.20; however, where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. See MPEP §2144.05 II A; see also In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
In the case at hand, YANG teaches the general conditions of claim 10. Specifically, the field indicated by YANG regarding the dimensions such as a ratio of the thickness of the gate structure to a thickness of the plurality of lightly doped portions is the variable describe by the range is "result-effective," i.e. the prior art discloses/teaches that the range/variable in question is one that, which changed, results in a demonstrable/desired effect. For instance, a ratio of the thickness of the gate structure to a thickness of the plurality of lightly doped portions can be changed to the effect of having a desirable device characteristics, to control the leakage current. Therefore, one having ordinary skill in the at the time the application at hand would find it obvious to discover the optimum or workable ranges, for example, a ratio of the thickness of the gate structure to a thickness of the plurality of lightly doped portions is between about 3.50 and about 2.20 using only routine skill in the art.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20130130460 A1 – Figure 2B
STATEMENT OF RELEVANCE – A plurality of light doped drain (LDD) implant processes by using the dummy gates 206 and 207, thereby two LDDs, 220a and 221a are respectively formed I the N well region, 201a and the P well region, 201b.
US 20190043725 A1 – Figure 4
STATEMENT OF RELEVANCE – A plurality of spacers, a first spacer, 24 and the second spacer, 36 are aligned with the gate structure, and are preferably made of different material.
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/SESHA SAIRAMAN SRINIVASAN/ Examiner, Art Unit 2817
/ALI NARAGHI/ Primary Examiner, Art Unit 2817
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