DETAILED ACTION
Claim Rejections - 35 USC § 102
1. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
2. Claim(s) 1, 9 -11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Fukasawa (9859214).
With regard to claim 1, Fukasawa discloses a structure (for example, see fig. 1), comprising:
a first conductive component (22);
a first interlayer dielectric (24) disposed adjacent to the first conductive component (22) in a cross-sectional side view;
a material layer (referred to as “30A” by examiner’s annotation shown in fig. 1 below) disposed over a first portion of an upper surface of the first conductive component (22) such that a bottom surface of the material layer (30A) extends to the first portion of the upper surface of the first conductive component (22) in the cross-sectional side view, and wherein the material layer (30A) is vertically overlaid with the first conductive component (22);
a second conductive component (43 or 40) disposed over a second portion of the upper surface of the first conductive component (22) in the cross-sectional side view; and
a dielectric layer (referred to as “30B” by examiner’s annotation shown in fig. 1 below; wherein the dielectric layer 30B including portions of the layers 14, 30) disposed over an upper surface of the first ILD (24) in the cross-sectional side view;
wherein the dielectric layer (30B) and the material layer (30A) have co-planar bottom surfaces; and
wherein the dielectric layer (referred to as “30B” by examiner’s annotation shown in fig. 1 below; wherein the dielectric layer 30B including portions of the layers 14, 30 wherein the portion layer 14 including an insulating material) and the material layer (the material layer 30A is a portion of the layer 30, wherein the material layer 30A made of adhesive material) inherently have different material compositions (based on the different compositions of the different layers 30, 14).
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With regard to claim 10, Fukasawa discloses a portion of the dielectric layer (30B) is disposed directly below a portion of the second conductive component (43).
With regard to claim 11, Fukasawa discloses an etching stop layer (referred to as “14C” by examiner’s annotation shown in fig. 1 below) disposed over (above or over the sidewall) both the material layer (30A) and the dielectric layer (30B) in the cross-sectional side view; and a second ILD (11) disposed over the etching stop layer (14C) in the cross-sectional side view; wherein: a first portion (referred to as “43A” by examiner’s annotation shown in fig. 1 below) of a side surface (a sidewall surface) of the second conductive component (40) is in contact with the second ILD (11) in the cross-sectional side view; a second portion (referred to as “43B” by examiner’s annotation shown in fig. 1 below) of a side surface (a sidewall surface) of the second conductive component (40) is in contact with the etching stop layer (14C) in the cross-sectional side view; and a first portion (42) of a side surface of the second conductive component (40) is in contact with the material layer (30A) in the cross-sectional side view.
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With regard to claim 9, Fukasawa discloses a height of the dielectric layer (30B) is greater than a height of the material layer (30A).
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Claim Rejections - 35 USC § 103
3. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claim(s) 2 – 7, 18, 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fukasawa (9859214) in view of DREES et al. (2018/0244978).
With regard to claim 2, Fukasawa does not clearly disclose the material layer includes a head group and a tail group wherein the material layer includes a plurality of strands; and each strand includes a member of the head group and a member of the tail group.
However, DREES et al. disclose the material layer includes a head group and a tail group wherein the material layer includes a plurality of strands; and each strand includes a member of the head group and a member of the tail group. (for example, see paragraphs [0004], [0006], figs. 1, 2).
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Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to have modified the Fukasawa’s device to have the material layer includes a head group and a tail group wherein the material layer includes a plurality of strands; and each strand includes a member of the head group and a member of the tail group as taught by DREES et al. in order to prevent damage to the conductive component and enhancing the reliability of the electrical connection between the vias and the conductive component for a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
With regard to claim 3, DREES et al. disclose the head group is bonded with the first conductive component (the substrate comprises a noble metal material, functioning as first conductive component; for example, see paragraph [0006]). It would have been obvious to one of ordinary skill in the art at the time the invention was made to have modified the Fukasawa’s device to have the head group is bonded with the first conductive component as taught by DREES et al. in order to prevent damage to the conductive component and enhancing the reliability of the electrical connection between the vias and the conductive component for a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
With regard to claim 4, DREES et al. disclose the head group has an affinity with a material of the first conductive component (the substrate comprises a noble metal material, functioning as first conductive component; for example, see paragraph [0006]), but inherently not with a material of the first ILD (no ILD layer forming around thereon). It would have been obvious to one of ordinary skill in the art at the time the invention was made to have modified the Fukasawa’s device to have the head group has an affinity with a material of the first conductive component as taught by DREES et al. in order to prevent damage to the conductive component and enhancing the reliability of the electrical connection between the vias and the conductive component for a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
With regard to claim 5, DREES et al. disclose the head group contains silicon (the head made of S-H, wherein S-H comprising silicon material; for example, see paragraph [0006]) or phosphonates including phosphorous material. It would have been obvious to one of ordinary skill in the art at the time the invention was made to have modified the Fukasawa’s device to have the head group contains silicon as taught by DREES et al. in order to prevent damage to the conductive component and enhancing the reliability of the electrical connection between the vias and the conductive component for a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
With regard to claim 6, DREES et al. disclose the tail group contains a thermodynamically stable material. (Paragraph [0098] discloses strong bonds and are stable over a wide range of temperatures, and it is inherently the tail group contains a thermodynamically stable material based on strong bonds and are stable over a wide range of temperatures). It would have been obvious to one of ordinary skill in the art at the time the invention was made to have modified the Fukasawa’s device to have the tail group contains a thermodynamically stable material as taught by DREES et al. in order to prevent damage to the conductive component and enhancing the reliability of the electrical connection between the vias and the conductive component for a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
With regard to claim 7, DREES et al. disclose the tail group contains an organic material. (for example, see paragraph [0006], or self-assembled monolayers including the tail group contains an organic material, heterocycles material functioning as an organic material; for example, see paragraph [0097]). It would have been obvious to one of ordinary skill in the art at the time the invention was made to have modified the Fukasawa’s device to have the tail group contains an organic material as taught by DREES et al. in order to prevent damage to the conductive component and enhancing the reliability of the electrical connection between the vias and the conductive component for a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
With regard to claim 18, Fukasawa discloses a structure (for example, see fig. 1), comprising:
a first conductive component (22);
a first interlayer dielectric (24) disposed adjacent to the first conductive component (22) to a cross-sectional side view;
a material layer (referred to as “30A” by examiner’s annotation shown in fig. 1 below) disposed over a first portion of an upper surface of the first conductive component (22) in the cross-sectional side view,
a second conductive component (43 or 40) disposed over a second portion of the upper surface of the first conductive component (22) in the cross-sectional side view;
a dielectric layer (referred to as “30B” by examiner’s annotation shown in fig. 1 below) disposed over an upper surface of the first ILD (24) in the cross-sectional side view;
wherein the dielectric layer (referred to as “30B” by examiner’s annotation shown in fig. 1 below; wherein the dielectric layer 30B including portions of the layers 14, 30 wherein the portion layer 14 including an insulating material) and the material layer (the material layer 30A is a portion of the layer 30, wherein the material layer 30A made of adhesive material) inherently have different material compositions (based on the different compositions of the different layers 30, 14);
an etching stop layer (referred to as “14C” by examiner’s annotation shown in fig. 1 below) disposed over the dielectric layer (30B) and over the material layer (30A) in the cross-sectional side view, wherein a bottom surface of a first portion of the etching stop layer (14C) extends to an upper surface of the dielectric layer (30B); and wherein a bottom surface of a second portion of the etching stop layer (14C) extends to an upper surface of the material layer (30A) and
a second ILD (11) disposed over the etching stop layer (14C) in the cross-sectional side view.
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Fukasawa does not clearly disclose the material layer includes a plurality of strands, and wherein each of the strands includes a head group having an affinity with a material of the first conductive component and a tail group that contains an organic material
However, DREES et al. disclose the material layer includes a plurality of strands, and wherein each of the strands includes a head group (as shown in fig. 2 below) having an affinity with a material of the first conductive component (the substrate comprises a noble metal material, functioning as first conductive component; for example, see paragraph [0006]) and a tail group that contains an organic material (for example, see paragraph [0006], or self-assembled monolayers including the tail group contains an organic material, heterocycles material functioning as an organic material; for example, see paragraph [0097]).
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Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to have modified the Fukasawa’s device to have the material layer includes a plurality of strands, and wherein each of the strands includes a head group having an affinity with a material of the first conductive component and a tail group that contains an organic material as taught by DREES et al. in order to prevent damage to the conductive component and enhancing the reliability of the electrical connection between the vias and the conductive component for a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
With regard to claim 21, Fukasawa discloses a first portion (referred to as “30B1” by examiner’s annotation shown in fig. 1 below) of an upper surface of the dielectric layer (30B) directly contacts the second conductive component (40), and wherein the bottom surface of a first portion of the etching stop layer (14C) directly contacts a second portion (referred to as “30B2” by examiner’s annotation shown in fig. 1 below) of the upper surface of the dielectric layer (30B).
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5. Claim(s) 13 – 17, 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fukasawa (10157837) in view of DREES et al. (2018/0244978) and further in view of Wu et al. (9837306).
With regard to claim 13, Fukasawa discloses a structure (for example, see fig. 1), comprising:
a first conductive component (component 22 as shown in fig. 1 below) of an interconnect structure (a structure comprising the component 22 and a structure layer 21);
a first interlayer dielectric (24) surrounding side surfaces and a bottom surface (referred to as “22A” by examiner’s annotation shown in fig. 1 below) of the first conductive component (22) in a cross-sectional side view;
a material layer (referred to as “14B” by examiner’s annotation shown in fig. 1 below) disposed over a first portion (referred to as “22B” by examiner’s annotation shown in fig. 1 below) of an upper surface of the first conductive component (22) in the cross-sectional side view,
a second conductive component (43) disposed over a second portion (referred to as “22C” by examiner’s annotation shown in fig. 1 below) of the upper surface of the first conductive component (22) in the cross-sectional side view; wherein an upper surface of the material layer (14B) is free of being covered by the second conductive component (43).
a dielectric layer (referred to as “14D” by examiner’s annotation shown in fig. 1 below) disposed over an upper surface of the first ILD (24) in the cross-sectional side view;
wherein the dielectric layer (referred to as “14D” by examiner’s annotation shown in fig. 1 below; wherein the dielectric layer 14D including portions of the layers 14, 30 wherein the portion layer 30 including an adhesive material) and the material layer (the material layer 14B is a portion of the layer 14, wherein the material layer 14B made of an insulating material) inherently have different material compositions (based on the different compositions of the different layers 30, 14);
wherein the dielectric layer (14D) is thicker than the material layer (14B),
a second ILD (11) disposed over the dielectric layer (14D) and over the first portion (22B) of the upper surface of the first conductive component (22) in the cross-sectional side view, wherein the second ILD (11) surrounds side surfaces of the second conductive component (43) in the cross-sectional side view.
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Fukasawa does not clearly disclose the material layer is arranged into a plurality of strands, wherein each strand includes a head group that is attached to the first portion of the upper surface of the first conductive component, and wherein each strands further includes a tail group coupled to the head group.
However, DREES et al. disclose the material layer is arranged into a plurality of strands, wherein each strand includes a head group (as shown in fig. 2 below) that is attached to the first portion of the upper surface of the first conductive component (the substrate comprises a noble metal material, functioning as first conductive component; for example, see paragraph [0006]), and wherein each strands further includes a tail group (as shown in fig. 2 below) coupled to the head group (for example, see paragraphs [0004], [0006], figs. 1, 2).
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Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to have modified the Fukasawa’s device to have the material layer is arranged into a plurality of strands, wherein each strand includes a head group that is attached to the first portion of the upper surface of the first conductive component, and wherein each strands further includes a tail group coupled to the head group as taught by DREES et al. in order to prevent damage to the conductive component and enhancing the reliability of the electrical connection between the vias and the conductive component for a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
Fukasawa and DREES et al. do not clearly disclose the dielectric layer contains aluminum.
However, Wu et al. disclose the dielectric layer (130) contains aluminum. (for example, see column 5, lines 56, 57, fig. 1F).
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Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to have modified the Fukasawa and DREES et al.’s device to have the dielectric layer contains aluminum as taught by Wu et al. in order to prevent damage to the conductive component and enhancing the reliability of the electrical connection between the vias and the conductive component for a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
With regard to claim 14, DREES et al. disclose the head group contains silicon (the head made of S-H, wherein S-H comprising silicon material; for example, see paragraph [0006]) or phosphonates including phosphorous material; wherein the tail group contains a carbon chain. (for example, paragraph [0006], chain, (C—C)).
With regard to claim 15, Wu et al. disclose the second conductive component (180, 190) and the material layer (the layer 130, Fig. 1F functioning as the material layer) have substantially co-planar bottom surfaces.
With regard to claim 16, Wu et al. disclose the dielectric layer (130), has a thickness of 50 angstrom, for example, see column 3, lines 50 – 55, is thicker than the material layer (the dielectric layer 140 functioning as the material layer), has a thickness of 30, for example, see column 4, lines 7 – 8.
With regard to claim 17, Fukasawa discloses an etching stop layer (referred to as “14C” by examiner’s annotation shown in fig. 1 above) disposed over (above or over the sidewall) the material layer (14B) and the dielectric layer (14D) but below the second ILD (11) in the cross-sectional side view.
With regard to claim 19, Fukasawa and DREES et al. do not clearly disclose the dielectric layer has a greater vertical dimension than the material layer in the cross-sectional side view.
However, Wu et al. disclose the dielectric layer (140), has a thickness of 1000 angstroms,
for example, see column 4, lines 7 — 8, has a greater vertical dimension than the material layer (a layer 130 functioning as the material layer, has a thickness of 50 angstroms, for example, see
column 3, lines 50 —55), in the cross-sectional side view. (for example, see column 5, lines 56, 57, fig. 1F).
Therefore, it would have been obvious to one of ordinary skill in the art at the time the
invention was made to have modified the Fukasawa and DREES et al.’s device to have the
dielectric layer has a greater vertical dimension than the material layer in the cross-sectional side
view as taught by Wu et al. in order to in order to minimize the signal interference for enhancing
a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
6. Claim(s) 8, 20 are rejected under 35 U.S.C. 103 as being unpatentable over Fukasawa (10157837) in view of DREES et al. (20180244978) and further in view of Leggett (2005/0048411).
With regard to claims 8, 20, DREES et al. disclose the head group contains silicon (the head made of S-H, wherein S-H comprising silicon material; for example, see paragraph [0006]) or phosphonates including phosphorous material, but Fukasawa and DREES et al. do not clearly disclose the tail group contains a methyl group.
However, Leggett disclose the tail group contains a methyl group. (for example, see paragraphs [0005], [0006], fig. 2(c)).
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Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to have modified the Fukasawa’s device to have the tail group contains a methyl group as taught by Leggett in order to prevent damage to the conductive component and enhancing the reliability of the electrical connection between the vias and the conductive component for a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
Response to Amendment
7. Applicant's arguments with respect to claims have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
8. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
9. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TAN N TRAN whose telephone number is (571) 272 - 1923. The examiner can normally be reached on 8:30-5:00PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached on (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TAN N TRAN/
Primary Examiner, Art Unit 2812
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