Prosecution Insights
Last updated: July 17, 2026
Application No. 18/678,538

Semiconductor Device

Non-Final OA §102
Filed
May 30, 2024
Priority
Jul 24, 2015 — JP 2015-146351 +3 more
Examiner
AHMADI, MOHSEN
Art Unit
Tech Center
Assignee
Semiconductor Energy Laboratory Co., Ltd.
OA Round
1 (Non-Final)
87%
Grant Probability
Favorable
1-2
OA Rounds
1m
Est. Remaining
96%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allowance Rate
400 granted / 462 resolved
+26.6% vs TC avg
Moderate +10% lift
Without
With
+9.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
26 currently pending
Career history
487
Total Applications
across all art units

Statute-Specific Performance

§101
0.8%
-39.2% vs TC avg
§103
74.4%
+34.4% vs TC avg
§102
14.4%
-25.6% vs TC avg
§112
3.6%
-36.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 462 resolved cases

Office Action

§102
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION This action is responsive to the application No. 18/678,538 filed on 05/30/2024. Priority Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file. Information Disclosure Statement Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-8 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by (US Pub # 2016/0343866 to Koezuka et al. (Koezuka). The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. Regarding independent claim 1, Koezuka disclose a semiconductor device (Fig. 6B) comprising: a transistor (Fig. 6A: 150B); and a first insulating film (Fig. 6B; 116) over the transistor, wherein the transistor (150B) comprises: an oxide semiconductor film (108) over the first insulating film (104); a second insulating film (110) over the oxide semiconductor film (108); a metal oxide film (112) over the second insulating film (110); and a gate electrode (114) over the metal oxide film (112), wherein both end portions of the second insulating film (110) are inward from both end portions of the oxide semiconductor film (108) in a channel length direction of the transistor (150B), wherein both end portions of the metal oxide film (112) are inward from both the end portions of the second insulating film (110) in the channel length direction of the transistor, wherein the first insulating film (116) is in contact with a top surface and a side surface of the gate electrode (114), a side surface of the metal oxide film (112), a side surface of the second insulating film (110), and a part of a top surface of the second insulating film (110), wherein the first insulating film (116) comprises at least one of nitrogen, hydrogen, and fluorine (¶0088), wherein the oxide semiconductor film (108) comprises a channel region (108i) overlapping with the gate electrode (114) with the second insulating film (110) and the metal oxide film (112) therebetween, a source region in contact with the first insulating film, and a drain region in contact with the first insulating film, and wherein each of the source region (108s) and the drain region (108d) comprises at least one of hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, and a rare gas (¶0093 and 0126). Regarding claim 2, Koezuka discloses wherein the oxide semiconductor film comprises In, GA, and Zn (¶0019). Regarding claim 3, Koezuka discloses wherein when an electron beam with a probe diameter of 1 nm is incident on the oxide semiconductor film, a plurality of spots are observed in a ring-like region with high luminance in an electron diffraction pattern (¶0324-0325). Regarding claim 4, Koezuka discloses wherein the metal oxide film comprises at least one of In, Zn, Al, Ga, Y, and Sn (¶0103 and 0476). Regarding independent claim 5, Koezuka disclose a semiconductor device (Fig. 6B) comprising: a transistor (Fig. 6A: 150B); and a first insulating film (Fig. 6B; 116) over the transistor, wherein the transistor (150B) comprises: a first gate electrode (106); a second insulating film (104) over the first gate electrode; an oxide semiconductor film (108) over the second insulating film; a third insulating film (110) over the oxide semiconductor film; a metal oxide film (112) over the third insulating film; and a second gate electrode (114) over the metal oxide film, wherein both end portions of the third insulating film (110) are inward from both end portions of the oxide semiconductor film (108) in a channel length direction of the transistor (150B), wherein both end portions of the metal oxide film (112) are inward from both the end portions of the third insulating film (110) in the channel length direction of the transistor (150B), wherein the first insulating film (116) is in contact with a top surface and a side surface of the second gate electrode (114), a side surface of the metal oxide film (112), a part of a top surface of the third insulating film (110), and a side surface of the third insulating film (110), wherein the first insulating film (116) comprises at least one of nitrogen, hydrogen, and fluorine (see at least ¶0122), wherein the oxide semiconductor film (108) comprises a channel region (108i), a source region (108s) in contact with the first insulating film (116), and a drain region (108d) in contact with the first insulating film (116), wherein the second gate electrode (114) comprises a region overlapping with the first gate electrode (106) with the metal oxide film (112), the third insulating film (110), the oxide semiconductor film (108), and the second insulating film (104) therebetween, wherein each of the source region (108s) and the drain region (108d) comprises at least one of hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, and a rare gas (¶0093 and 0137), and wherein the second gate electrode (114) is connected to the first gate electrode (106) through an opening portion (Fig. 6C: 143) in the metal oxide film (112), the third insulating film (110), and the second insulating film (104). Regarding claim 6, Koezuka discloses wherein the oxide semiconductor film comprises In, GA, and Zn (¶0019). Regarding claim 7, Koezuka discloses wherein when an electron beam with a probe diameter of 1 nm is incident on the oxide semiconductor film, a plurality of spots are observed in a ring-like region with high luminance in an electron diffraction pattern (¶0324-0325). Regarding claim 8, Koezuka discloses wherein the metal oxide film comprises at least one of In, Zn, Al, Ga, Y, and Sn (¶0103 and 0476). Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US Pub # 2015/0221678 to Yamazaki et al. (Yamazaki). Regarding independent claim 1, Yamazaki disclose a semiconductor device (Fig. 1C) comprising: a transistor (Fig. 1C: 100 and ¶0083); and a first insulating film (118 and ¶0085) over the transistor, wherein the transistor (100) comprises: an oxide semiconductor film (110) over the first insulating film (118); a second insulating film (112) over the oxide semiconductor film (110); a metal oxide film (114a and ¶0161) over the second insulating film (112); and a gate electrode (114b) over the metal oxide film (114a), wherein both end portions of the second insulating film (112) are inward from both end portions of the oxide semiconductor film (110) in a channel length direction of the transistor (100), wherein both end portions of the metal oxide film (114a) are inward from both the end portions of the second insulating film (112) in the channel length direction of the transistor (100), wherein the first insulating film (118) is in contact with a top surface and a side surface of the gate electrode (114b), a side surface of the metal oxide film (114a), a side surface of the second insulating film (112), and a part of a top surface of the second insulating film (112), wherein the first insulating film (118) comprises at least one of nitrogen, hydrogen, and fluorine (¶0194), wherein the oxide semiconductor film (110) comprises a channel region (¶0078 and element 110a) overlapping with the gate electrode (114b) with the second insulating film (112) and the metal oxide film (114a) therebetween, a source region (110f) in contact with the first insulating film (118), and a drain region (110g) in contact with the first insulating film (118), and wherein each of the source region (110f) and the drain region (110g) comprises at least one of hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, and a rare gas (¶0018 and 0159). Regarding claim 2, Yamazaki discloses wherein the oxide semiconductor film comprises In, GA, and Zn (¶0140). Regarding claim 3, Yamazaki discloses wherein when an electron beam with a probe diameter of 1 nm is incident on the oxide semiconductor film, a plurality of spots are observed in a ring-like region with high luminance in an electron diffraction pattern (¶0335, 0348 and 0359 and Figs. 18A-18B). Regarding claim 4, Yamazaki discloses wherein the metal oxide film (114a) comprises at least one of In, Zn, Al, Ga, Y, and Sn (¶0161). Regarding independent claim 5, Yamazaki disclose a semiconductor device (Fig. 1C) comprising: a transistor (Fig. 1C: 100 and ¶0083); and a first insulating film (118 and ¶0085) over the transistor, wherein the transistor (100) comprises: a first gate electrode (Fig. 6: 106 and see ¶0167); a second insulating film (108) over the first gate electrode (Fig. 6: 106); an oxide semiconductor film (110) over the second insulating film (108); a third insulating film (112) over the oxide semiconductor film (110); a metal oxide film (114a and ¶0161) over the third insulating film; and a second gate electrode (114b) over the metal oxide film, wherein both end portions of the third insulating film (112) are inward from both end portions of the oxide semiconductor film (110) in a channel length direction of the transistor (100), wherein both end portions of the metal oxide film (114a) are inward from both the end portions of the third insulating film (112) in the channel length direction of the transistor (100), wherein the first insulating film (118) is in contact with a top surface and a side surface of the second gate electrode (114b), a side surface of the metal oxide film (114a), a part of a top surface of the third insulating film (112), and a side surface of the third insulating film (112), wherein the first insulating film (118) comprises at least one of nitrogen, hydrogen, and fluorine (¶0194), wherein the oxide semiconductor film (110) comprises a channel region (¶0078 and element 110a), a source region (110f) in contact with the first insulating film (118), and a drain region (110g) in contact with the first insulating film (118), wherein the second gate electrode (114b) comprises a region overlapping with the first gate electrode (Fig. 6: 106) with the metal oxide film (114a), the third insulating film (112), the oxide semiconductor film (110), and the second insulating film (108) therebetween, wherein each of the source region (110f) and the drain region (110g) comprises at least one of hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, and a rare gas (¶0018 and 0159), and wherein the second gate electrode (Fig. 6: 114b) is connected to the first gate electrode (Fig. 6: 106) through an opening portion (Fig. 6: 139) in the metal oxide film (114a), the third insulating film (112), and the second insulating film (108). Regarding claim 6, Yamazaki discloses wherein the oxide semiconductor film comprises In, GA, and Zn (¶0140). Regarding claim 7, Yamazaki discloses wherein when an electron beam with a probe diameter of 1 nm is incident on the oxide semiconductor film, a plurality of spots are observed in a ring-like region with high luminance in an electron diffraction pattern (¶0335, 0348 and 0359 and Figs. 18A-18B). Regarding claim 8, Yamazaki discloses wherein the metal oxide film (114a) comprises at least one of In, Zn, Al, Ga, Y, and Sn (¶0161). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Koezuka et al. (US Pub # 2012/0315735), Yamazaki et al. (US Pub # 2013/0187152), Isobe (US Pub # 2013/0203214), Yamazaki et al. (US Pub # 2015/0102341), Yamazaki et al. (US Pub # 2014/0339545), Yamazaki et al. (U.S. Pub # 2010/0025675). Koezuka discloses a semiconductor device (see FIG. 1A-1E) comprising, a semiconductor film (oxide semiconductor film 403) over a first insulating film (insulating film 436), a second insulating film (gate insulating film 402) over the semiconductor film (oxide semiconductor film 403), (see paragraphs [0115] & [0116], Koezuka teaches that the gate electrode layer 401 can comprise a stacked-layer structure formed of a conductive material such as indium-tin-oxide, and a metal material, such as tungsten and aluminum.), wherein the semiconductor film comprises a channel region 409 overlapping with the gate electrode, wherein the third insulating film 407 is a nitride film (see paragraph [0122], e.g., silicon oxynitride film) containing at least one of hydrogen and fluorine (see paragraphs [0128] & [0127], insulating film 407 may include dopant, including fluorine). Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHSEN AHMADI whose telephone number is (571)272-5062. The examiner can normally be reached M-F: 9:00am-5:00pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William F Kraig can be reached at 571-272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MOHSEN AHMADI/ Primary Examiner, Art Unit 2896
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Prosecution Timeline

May 30, 2024
Application Filed
Jun 11, 2026
Non-Final Rejection mailed — §102 (current)

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Prosecution Projections

1-2
Expected OA Rounds
87%
Grant Probability
96%
With Interview (+9.8%)
2y 3m (~1m remaining)
Median Time to Grant
Low
PTA Risk
Based on 462 resolved cases by this examiner. Grant probability derived from career allowance rate.

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