DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) filed on May 30, 2024 has been considered by the examiner.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed on June 21, 2024.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee (US 2023/0328950 A1).
Claim 1, Lee discloses a semiconductor device (semiconductor memory device 100 is a semiconductor device, hereinafter, semiconductor device 100, [0020] and [0064], Figs. 1, 2A, and 9) comprising:
a substrate (substrate 101, [0021], Fig. 2A);
a plurality of bit lines (a plurality of first bit lines BL1 is a plurality of bit lines, hereinafter, plurality of bit lines BL1, [0044], Fig. 2A) located on the substrate 101 (plurality of bit lines BL1 are located on the substrate 101, [0044], Fig. 2A) and disposed in parallel in a first horizontal direction (first direction D1 is a first horizontal direction, hereinafter, first horizontal direction D1, [0020], Fig. 2A) at predetermined intervals (plurality of bit lines BL1 are disposed in parallel in a first horizontal direction D1 at predetermined intervals, [0020] and [0044], Fig. 2A);
a plurality of word lines (second gate electrode 180 forms a plurality of word lines WL, hereinafter, plurality of word lines WL, [0042], Fig. 2A) located on the bit lines BL1 (plurality of word lines WL are located on the bit lines BL1, [0042], Fig. 2A) and disposed in parallel in a second horizontal direction (second direction D2 is a second horizontal direction, hereinafter, second horizontal direction D2, [0042], Fig. 2A) substantially perpendicular to the first horizontal direction D1 (second horizontal direction D2 is substantially perpendicular to the first horizontal direction D1, [0020], Fig. 2A) at predetermined intervals (plurality of word lines WL are disposed in parallel in a second horizontal direction D2 at predetermined intervals, [0042], Fig. 2A);
a plurality of channel patterns (first channel region CH1 overlaps recess R in plan view and is a plurality of channel patterns, hereinafter, plurality of channel patterns CH1, [0019] and [0023], Figs. 1 and 2A) located on the bit lines BL1 (plurality of channel patterns CH1 are located on the bit lines BL1, [0019] and [0023], Figs. 1 and 2A), spaced apart in a third horizontal direction different from the first and second horizontal directions (plurality of channel patterns CH1 are spaced apart in a third horizontal direction HD3 different from the first and second horizontal directions D1/D2, [0019] and [0023], Annotated Fig. 1 and Fig. 2A) and a fourth horizontal direction substantially perpendicular to the third horizontal direction HD3 (plurality of channel patterns CH1 are spaced apart in a fourth horizontal direction HD4 substantially perpendicular to the third horizontal direction HD3, [0019] and [0023], Annotated Fig. 1 and Fig. 2A), and extending in a vertical direction (plurality of channel patterns CH1 extend in a third direction D3 which is a vertical direction, hereinafter, vertical direction D3, [0019] and [0023], Figs. 1 and 2A);
a gate insulating pattern (gate insulating layer 130 is a gate insulating pattern, hereinafter, gate insulating pattern 130, [0027] and [0066], Figs. 2A and 9) located between the plurality of channel patterns CH1 and the plurality of word lines WL (gate insulating pattern 130 is located between the plurality of channel patterns CH1 and the plurality of word lines WL, [0027] and [0066], Figs. 2A and 9);
a plurality of switching insulating layers (pillar structure PS includes a plurality of switching insulating layers, hereinafter, plurality of switching insulating layers PS, [0032], Fig. 9) respectively formed on upper surfaces of the plurality of channel patterns CH1 (plurality of switching insulating layers PS are respectively formed on upper surfaces of the plurality of channel patterns CH1, [0032], Fig. 9), at least a portion of which has a thickness that an electron can penetrate upon application of a voltage (at least a portion of plurality of switching insulating layers PS has a thickness that an electron can penetrate upon application of a voltage, [0034], Fig. 9); and
a plurality of control electrodes (second connection electrode layers 150b are a plurality of control electrodes, hereinafter, plurality of control electrodes 150b, [0043], Figs. 2A and 9) disposed in parallel at predetermined intervals to connect the plurality of switching insulating layers PS (plurality of control electrodes 150b are disposed in parallel at predetermined intervals to connect the plurality of switching insulating layers PS, [0043], Figs. 2A and 9).
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Annotated Fig. 1 (Lee) – Illustrates a plurality of bit lines BL1 located on the substrate 101 and disposed in parallel in a first horizontal direction D1 at predetermined intervals, a plurality of word lines WL located on the bit lines BL1 and disposed in parallel in a second horizontal direction D2 substantially perpendicular to the first horizontal direction D1 at predetermined intervals, a plurality of channel patterns CH1 located on the bit lines BL1, spaced apart in a third horizontal direction HD3 different from the first and second horizontal directions D1/D2, and a fourth horizontal direction HD4 substantially perpendicular to the third horizontal direction HD3.
Claim 2, Lee discloses the semiconductor device (semiconductor device 100, [0020] and [0064], Figs. 1, 2A, and 9) of claim 1.
Lee discloses wherein the plurality of control electrodes 150b are disposed in parallel in the second horizontal direction D2 (plurality of control electrodes 150b are disposed within each pillar structure PS which is in parallel in the second horizontal direction D2, [0043], Figs. 1 and 2A).
Claim 3, Lee discloses the semiconductor device (semiconductor device 100, [0020] and [0064], Figs. 1, 2A, and 9) of claim 1.
Lee discloses further comprising spacer layers (interlayer insulating layer 110 is a spacer layer, hereinafter, spacer layer 110, [0022], Figs. 2A) formed on at least portions of side surfaces of the plurality of channel patterns CH1 to electrically insulate the plurality of channel patterns CH1 and the plurality of control electrodes 150b (spacer layer 110 is formed on at least portions of side surfaces of the plurality of channel patterns CH1 to electrically insulate the plurality of channel patterns CH1 and the plurality of control electrodes 150b, [0022], Figs. 2A).
Claim 4, Lee discloses the semiconductor device (semiconductor device 100, [0020] and [0064], Figs. 1, 2A, and 9) of claim 1.
Lee discloses wherein, when an interval between adjacent word lines WL is L1, an interval between adjacent bit lines BL1 is L2, and an angle formed by the first horizontal direction and the third horizontal direction is θ1, tanθ1 is L2/L1 (i.e.
tan
(
θ
1
)
=
L
2
L
1
) (an interval between adjacent word lines WL is L1, an interval between adjacent bit lines BL1 is L2, and an angle formed by the first horizontal direction D1 and the third horizontal direction HD3 is θ1,
tan
(
θ
1
)
=
L
2
L
1
, [0020], Annotated Fig. 1*).
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Annotated Fig. 1* (Lee) – Illustrates when an interval between adjacent word lines WL is L1, an interval between adjacent bit lines BL1 is L2, and an angle formed by the first horizontal direction D1 and the third horizontal direction HD3 is θ1,
tan
(
θ
1
)
=
L
2
L
1
.
Claim 5, Lee discloses the semiconductor device (semiconductor device 100, [0020] and [0064], Figs. 1, 2A, and 9) of claim 4.
Lee discloses wherein L1 and L2 are substantially the same (L1 and L2 are substantially the same, [0020], Annotated Fig. 1*).
Claim 6, Lee discloses the semiconductor device (semiconductor device 100, [0020] and [0064], Figs. 1, 2A, and 9) of claim 1.
Lee discloses wherein the plurality of channel patterns CH1 located on a single bit line BL1 are arranged in a straight line form in the first horizontal direction D1 (plurality of channel patterns CH1 located on a single bit line BL1 are arranged in a straight line form in the first horizontal direction D1, [0020], Annotated Fig. 1*).
Claim 7, Lee discloses the semiconductor device (semiconductor device 100, [0020] and [0064], Figs. 1, 2A, and 9) of claim 1.
Lee discloses wherein, when the total number of crossing points of the word lines and the bit lines is n1 (total number of crossing points of the word lines WL and the bit lines BL1/BL2 is n1, [0020], Annotated Fig. 1*), and the number of crossing points where the channel patterns are disposed is n2 (number of crossing points where the channel patterns CH1 are disposed is n2, [0020], Annotated Fig. 1*), n1/n2 is 2 (n1 = 18 and n2 = 9, wherein 18/9 = 2, Annotated Fig. 1**).
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Annotated Fig. 1** (Lee) – Illustrates wherein, when the total number of crossing points of the word lines WL and the bit lines BL1/BL2 is n1, and the number of crossing points where the channel patterns CH1 are disposed is n2; n1 = 18 and n2 = 9, wherein 18/9 = 2.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kim (US 2023/0048424 A1) discloses a memory cell MC in Fig. 2, further including a plurality of bit lines BL perpendicular to a plurality of word lines WL and disposed on a substrate SUB.
Lee (US 2023/0101700 A1) discloses a semiconductor memory device 100 in Figs. 1A/1B/1C, further including a plurality of bit lines BLC1/BLC2 perpendicular to a plurality of word lines WL and disposed on a substrate 1.
Sung (US 2012/0153365 A1) discloses a semiconductor device in Figs. 1 and 2I further including a plurality of bit lines 120a/120b perpendicular to a plurality of word lines 240a/240b and disposed on a substrate 100a/100b.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHEVY J BOEGEL whose telephone number is (703)756-1299. The examiner can normally be reached Monday - Friday 8:00 AM - 5:00 PM.
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/CHEVY J BOEGEL/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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