DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on January 15th, 2026 has been entered. By this amendment, claims 1 and 12 have been amended. Accordingly, claims 1-20 are pending in the present application in which claims 1, 12, and 18 are in independent form.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-3, 6-11, and 18-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,027,435. Although the claims at issue are not identical, they are not patentably distinct from each other because the scope of the claimed invention of the present application is encompassed by the scope of the claimed invention of U.S. Patent No. 12,027,435, see comparison table below.
Claims of present application
Claims of U.S. Patent No. 12,027,435
1. A structure comprising: a reconstructed package substrate comprising: a first substrate block free from active devices therein, the first substrate block comprising a first plurality of redistribution lines therein, wherein the first plurality of redistribution lines collectively form a conductive path; an encapsulant encapsulating the first substrate block therein, wherein the conductive path in the first substrate block extends all the way from a top surface level to a bottom surface level of the encapsulant; a redistribution structure overlapping the first substrate block and the encapsulant, wherein the redistribution structure comprises a second plurality of redistribution lines therein; and a plurality of conductive features underlying the first substrate block, wherein the plurality of conductive features are electrically connected to the redistribution structure through the first substrate block.
1. A structure comprising: a reconstructed package substrate comprising: a plurality of substrate blocks, each comprising a first plurality of redistribution lines and a conductive path therein; an encapsulant encapsulating the plurality of substrate blocks therein, wherein the plurality of substrate blocks are separated from each other by some portions of the encapsulant, and wherein the conductive path in each of the plurality of substrate blocks extends all the way from a top surface level to a bottom surface level of the encapsulant; a redistribution structure overlapping the plurality of substrate blocks and the encapsulant, wherein the redistribution structure comprises a second plurality of redistribution lines therein; and a plurality of conductive features underlying and electrically connected to the redistribution structure through the plurality of substrate blocks; and a first device die overlying and bonded to the reconstructed package substrate.
2. The structure of claim 1, wherein the first substrate block comprises a plurality of dielectric layers, wherein edges of the plurality of dielectric layers are vertically aligned, and wherein the edges are in contact with the encapsulant.
10. A structure comprising: a first dielectric layer; a plurality of conductive features in the first dielectric layer; an encapsulant overlying and contacting the first dielectric layer; a plurality of substrate blocks penetrating through the encapsulant, wherein the plurality of substrate blocks are overlying and contacting the first dielectric layer, and wherein each of the plurality of substrate blocks comprises an electrically conductive path comprising a top end and a bottom end, and the top end is coplanar with a top surface of the encapsulant, and the bottom end is coplanar with a bottom surface of the encapsulant; a second dielectric layer over and contacting both of the plurality of substrate blocks and the encapsulant…
3. The structure of claim 1, wherein the encapsulant comprises a molding compound.
18. The structure of claim 17, wherein the plurality of substrate blocks form vertical interfaces with the molding compound.
6. The structure of claim 1, wherein the first substrate block is free from active devices therein.
7. The structure of claim 1, wherein the plurality of substrate blocks are free from both of active devices and passive devices.
7. The structure of claim 1 further comprising a device die in the encapsulant, wherein top surfaces of the first substrate block and the device die are coplanar, and wherein a first bottom surface of the first substrate block is coplanar with a second bottom surface of the device die.
4. The structure of claim 1 further comprising a package component encapsulated in the encapsulant, wherein the package component is selected from a device die and an integrated passive device, and wherein the package component comprises additional conductive features electrically connected to the redistribution structure.
8. The structure of claim 7, wherein the bottom surface of the device die comprises a bottom surface of a semiconductor substrate of the device die.
Note that, it is well-known in the art that the device die is an active device die that includes a semiconductor substrate.
4. The structure of claim 1 further comprising a package component encapsulated in the encapsulant, wherein the package component is selected from a device die and an integrated passive device, and wherein the package component comprises additional conductive features electrically connected to the redistribution structure.
9. The structure of claim 7 further comprising a dielectric layer underlying and contacting both of first substrate block and the encapsulant.
5. The structure of claim 4 further comprising a dielectric layer underlying and contacting both of a first bottom surface of the package component and a second bottom surface of the encapsulant.
10. The structure of claim 1 further comprising a through-via penetrating through the encapsulant, wherein the plurality of conductive features are further electrically connected to the redistribution structure through the through-via.
3. The structure of claim 1 further comprising a through-via in the encapsulant, wherein one of the plurality of conductive features is electrically connected to the redistribution structure through the through-via.
11. The structure of claim 1 further comprising a second substrate block, wherein the plurality of conductive features are further electrically connected to the redistribution structure through the second substrate block.
20. The structure of claim 17 further comprising an additional package component penetrating through the molding compound.
18. A structure comprising: a substrate block free from active devices and passive devices therein, the substrate block comprising: a plurality of dielectric layers, wherein edges of the plurality of dielectric layers are joined to form a continuous-and-straight edge; electrical paths penetrating through the substrate block; a molding compound molding the substrate block therein, wherein the molding compound comprises: a top surface coplanar with top ends of the electrical paths; and a bottom surface coplanar with bottom ends of the electrical paths, wherein the continuous-and-straight edge extends from the top surface to the bottom surface; a device die over the substrate block; and a package component underlying and electrically connected to the device die through the electrical paths in the substrate block.
17. A structure comprising: a plurality of substrate blocks, each comprising: a plurality of dielectric layers; electrical paths through the plurality of dielectric layers, wherein the electrical paths extend from a first top surface to a first bottom surface of the respective one of the plurality of substrate blocks; a molding compound molding the plurality of substrate blocks therein, wherein the molding compound further comprises: a second top surface coplanar with top ends of the electrical paths; and a second bottom surface coplanar with bottom ends of the electrical paths; a plurality of device dies over the plurality of substrate blocks; and a package component underlying and electrically connected to the plurality of device dies through the electrical paths in the plurality of substrate blocks.
7. The structure of claim 1, wherein the plurality of substrate blocks are free from both of active devices and passive devices.
19. The structure of claim 18 further comprising: a first dielectric layer underlying and contacting the substrate block; and a second dielectric layer overlying and contacting the substrate block, wherein the continuous-and-straight edge has opposite ends contacting the first dielectric layer and the second dielectric layer.
10. A structure comprising: a first dielectric layer; a plurality of conductive features in the first dielectric layer; an encapsulant overlying and contacting the first dielectric layer; a plurality of substrate blocks penetrating through the encapsulant, wherein the plurality of substrate blocks are overlying and contacting the first dielectric layer, and wherein each of the plurality of substrate blocks comprises an electrically conductive path comprising a top end and a bottom end, and the top end is coplanar with a top surface of the encapsulant, and the bottom end is coplanar with a bottom surface of the encapsulant; a second dielectric layer over and contacting both of the plurality of substrate blocks…
20. The structure of claim 18 further comprising a through-via penetrating through the molding compound.
19. The structure of claim 17 further comprising a through-via penetrating through the molding compound.
Claims 4 and 5 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,027,435 in view of Tsai et al. (U.S. Pub. 2019/0157240).
In re claim 4, as applied to claim 3 above, claims of U.S. Patent No. 12,027,435 are silent to wherein the molding compound comprises a base material comprising a first planar top surface; and partial spherical particles comprising second planar top surfaces and rounded bottom surfaces, wherein the first planar top surface is coplanar with the second planar top surfaces.
However, Tsai discloses in a same field of endeavor, a structure including, inter-alia, a reconstructed package substrate comprising a substrate block, an encapsulant comprises a molding compound 48 encapsulating the substrate block therein, wherein the molding compound comprises a base material 48A comprising a first planar top surface; and partial spherical particles 48B comprising second planar top surfaces and rounded bottom surfaces, wherein the first planar top surface is coplanar with the second planar top surfaces (see paragraph [0023] and figs. 5 and 26).
Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art to be motivated to incorporate the technique as taught by Tsai into the claimed invention of U.S. Patent No. 12,027,435 in order to enable wherein the molding compound comprises a base material comprising a first planar top surface; and partial spherical particles comprising second planar top surfaces and rounded bottom surfaces, wherein the first planar top surface is coplanar with the second planar top surfaces to be formed in order to obtain a fan-out package having a greater throughput and lower cost (see paragraphs [0003], [0004] of Tsai) and the reliability of the RDLs is improved (see paragraph [0061] of Tsai).
In re claim 5, as applied to claim 4 above, claims of U.S. Patent No. 12,027,435 in combination with Tsai discloses wherein the base material 48A further comprises a first planar bottom surface, and wherein the partial spherical particles 48B further comprise second planar bottom surfaces and rounded top surfaces, and wherein the first planar bottom surface is coplanar with the second planar bottom surfaces (see paragraph [0024] and figs. 5 and 26 of Tsai).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-11 and 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (U.S. Pub. 2020/0411488) in view of Tsai et al. (U.S. Pub. 2019/0157240).
In re claim 1, Yu discloses a structure comprising a reconstructed package substrate comprising a first substrate block 84B free from active devices therein, the first substrate block 84B comprising a first plurality of redistribution lines therein (see paragraph [0040] and figs. 20-24, note that, the first substrate block 84B contains a plurality of conductive lines and is free from active devices therein), wherein the first plurality of redistribution lines collectively form a conductive path (see paragraph [0040] and figs. 20-24); wherein the conductive path in the first substrate block 84B extends all the way from a top surface level to a bottom surface level of the first substrate block 84B (see paragraph [0040] and figs. 20-24), a redistribution structure 84A overlapping the first substrate block 8B and the encapsulant 80, wherein the redistribution structure 84A comprises a second plurality of redistribution lines therein (see paragraph [0040] and figs. 20-24); and a plurality of conductive features 102 underlying the first substrate block 84B, wherein the plurality of conductive features 102 are electrically connected to the redistribution structure 84A through the first substrate block 84B (see paragraph [0042] and fig. 24).
PNG
media_image1.png
513
791
media_image1.png
Greyscale
Yu is silent to wherein an encapsulant encapsulating the first substrate block therein, wherein the conductive path in the first substrate block extends all the way from a top surface level to a bottom surface level of the encapsulant, and a redistribution structure overlapping the first substrate block and the encapsulant.
However, Tsai discloses in a same field of endeavor, a structure comprising a reconstructed package substrate, including, inter-alia, a first substrate block 36 (see paragraph [0021] and fig. 26), an encapsulant comprises 48 a molding structure encapsulating the first substrate block 36 therein, wherein the conductive path 32 in the first substrate block extends all the way from a top surface level to a bottom surface level of the encapsulant 48 (see paragraph [0023] and fig. 26), and a redistribution structure (71,76,78) overlapping the first substrate block 36 and the encapsulant 48 (see paragraphs [0037], [0038] and fig. 26).
Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the teaching as taught by Tsai into the structure of Yu in order to enable wherein an encapsulant encapsulating the first substrate block therein, wherein the conductive path in the first substrate block extends all the way from a top surface level to a bottom surface level of the encapsulant, and a redistribution structure overlapping the first substrate block and the encapsulant in Yu to be formed in order to obtain a fan-out package having a greater throughput and lower cost (see paragraphs [0003], [0004] of Tsai) and the reliability of the RDLs is improved (see paragraph [0061] of Tsai). Furthermore, it would have been obvious because all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of the invention. KSR International Co. v. Teleflex Inc. (KSR), 550 U.S. 398 (2007). “If a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond that person’s skill.” Id.
In re claim 2, as applied to claim 1 above, Yu in combination with Tsai discloses wherein the first substrate block comprises a plurality of dielectric layers, wherein edges of the plurality of dielectric layers are vertically aligned, and wherein the edges are in contact with the encapsulant 48 (see paragraph [0023] and fig. 26 of Tsai).
In re claim 3, as applied to claim 1 above, Yu in combination with Tsai discloses wherein the encapsulant comprises a molding compound (see paragraph [0023] and fig. 26 of Tsai).
In re claim 4, as applied to claim 3 above, Yu in combination with Tsai discloses wherein the molding compound 48 comprises a base material 48A comprising a first planar top surface; and partial spherical particles 48B comprising second planar top surfaces and rounded bottom surfaces, wherein the first planar top surface is coplanar with the second planar top surfaces (see paragraph [0023] and fig. 26 of Tsai).
In re claim 5, as applied to claim 4 above, Yu in combination with Tsai discloses wherein the base material 48A further comprises a first planar bottom surface, and wherein the partial spherical particles 48B further comprise second planar bottom surfaces and rounded top surfaces, and wherein the first planar bottom surface is coplanar with the second planar bottom surfaces (see paragraph [0023] and fig. 26 of Tsai).
In re claim 6, as applied to claim 1 above, Yu in combination with Tsai discloses wherein the first substrate block 84B is free from active devices therein (see paragraph [0040] and fig. 24 of Yu).
In re claim 7, as applied to claim 1 above, Yu in combination with Tsai discloses wherein the structure further comprising a device die (adjacent device die 36) in the encapsulant 48, wherein top surfaces of the first substrate block and the device die are coplanar, and wherein a first bottom surface of the first substrate block is coplanar with a second bottom surface of the device die (see paragraphs [0021], [0023] and fig. 26 of Tsai).
In re claim 8, as applied to claim 7 above, Yu in combination with Tsai discloses wherein the bottom surface of the device die comprises a bottom surface of a semiconductor substrate of the device die (see paragraph [0021] and fig. 26 of Tsai).
In re claim 9, as applied to claim 7 above, Yu in combination with Tsai discloses wherein the structure further comprising a dielectric layer 24 underlying and contacting both of first substrate block 36 and the encapsulant 48 (see paragraphs [0021], [0023] and fig. 26 of Tsai).
In re claim 10, as applied to claim 1 above, Yu in combination with Tsai discloses wherein the structure further comprising a through-via 32 penetrating through the encapsulant 48, wherein the plurality of conductive features 122 are further electrically connected to the redistribution structure (71,78) through the through-via 32 (see paragraph [0044] and fig. 26 of Tsai).
In re claim 11, as applied to claim 1 above, Yu in combination with Tsai discloses wherein the structure further comprising a second substrate block (adjacent substrate block 36), wherein the plurality of conductive features 122 are further electrically connected to the redistribution structure (71,76) through the second substrate block 36 (see paragraph [0021] and fig. 26 of Tsai).
In re claim 18, Yu discloses a structure comprising a substrate block 84B free from active devices and passive devices therein, the substrate block 84B comprising a plurality of dielectric layers 82B, wherein edges of the plurality of dielectric layers 82B are joined to form a continuous-and-straight edge (see paragraphs [0039], [0040] and fig. 24); electrical paths 84B penetrating through the substrate block (see paragraph [0040] and fig. 24), wherein the continuous-and-straight edge extends from the top surface to the bottom surface (see paragraph [0039] and fig. 24); a device die 112 over the substrate block 84B (see paragraph [0044] and fig. 24); and a package component 40 underlying and electrically connected to the device die 112 through the electrical paths in the substrate block 84B (see paragraphs [0019], [0040] and fig. 24).
Yu is silent to wherein a molding compound molding the substrate block therein, wherein the molding compound comprises a top surface coplanar with top ends of the electrical paths; and a bottom surface coplanar with bottom ends of the electrical paths.
However, Tsai discloses in a same field of endeavor, a structure comprising a substrate block, including, inter-alia, a molding compound 48 molding the substrate block 36 therein, wherein the molding compound 48 comprises a top surface coplanar with top ends of the electrical paths; and a bottom surface coplanar with bottom ends of the electrical paths (see paragraphs [0021], [0023] and fig. 26).
Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the teaching as taught by Tsai into the structure of Yu in order to enable wherein a molding compound molding the substrate block therein, wherein the molding compound comprises a top surface coplanar with top ends of the electrical paths; and a bottom surface coplanar with bottom ends of the electrical paths in Yu to be formed in order to obtain a fan-out package having a greater throughput and lower cost (see paragraphs [0003], [0004] of Tsai) and the reliability of the RDLs is improved (see paragraph [0061] of Tsai). Furthermore, it would have been obvious because all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of the invention. KSR International Co. v. Teleflex Inc. (KSR), 550 U.S. 398 (2007). “If a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond that person’s skill.” Id.
In re claim 19, as applied to claim 18 above, Yu in combination with Tsai discloses wherein the structure further comprising a first dielectric layer 24 underlying and contacting the substrate block 36; and a second dielectric layer 62 overlying and contacting the substrate block 36, wherein the continuous-and-straight edge has opposite ends contacting the first dielectric layer 24 and the second dielectric layer 62 (see paragraphs [0021], [0032] and fig. 26 of Tsai).
In re claim 20, as applied to claim 18 above, Yu in combination with Tsai discloses wherein the structure further comprising a through-via 32 penetrating through the molding compound 48 (see paragraphs [0018], [0023] and fig. 26 of Tsai).
Allowable Subject Matter
Claims 12-17 are allowed over prior art of record.
Reasons For Allowance
The following is an examiner’s statement of reasons for allowance:
It is determined that the prior art of record neither anticipates nor renders obvious the claimed subject matter of independent claim 12 as a whole taken alone or in combination, in particular, prior art of record does not teach “wherein the substrate block comprises an electrically conductive path comprising a top end coplanar with a top surface of the encapsulant, wherein the top end is a topmost end of a first conductive pad, and the first conductive pad is tapered with a first top width an a first bottom width smaller than the first top width and a bottom end coplanar with a bottom surface of the encapsulant, wherein the bottom end is a bottommost end of a second conductive pad, and the second conductive pad is tapered with a second top width and a second bottom width greater than the second top width", as recited in independent claim 12.
Claims 13-17 also allowed as being directly or indirectly dependent of the allowed independent base claim.
Response to Applicant’s Amendment and Arguments
Applicant's arguments filed January 15th, 2026 have been fully considered but they are not persuasive.
With respect to independent claim 1 and similarly to independent claim 18, Applicant contends that Yu in combination with Tsai does not teach or suggest the limitations of a first substrate block free from active devices therein, the first substrate block comprising a plurality of redistribution lines therein, wherein the first plurality of redistribution lines collectively form a conductive path and an encapsulant encapsulating the first substrate block therein, wherein the conductive path in the first substrate block extends all the way from a top surface level to a bottom surface level of the encapsulant.
However, it is respectfully submitted that Applicant’s above argument is not persuasive because Yu discloses in paragraphs [0028], [0040], [0044] and fig. 24, a first substrate block 84B comprising a plurality of redistribution lines therein and collectively forming a conductive path for electrically connecting power modules 112 and package components 40, the first substrate block 84B is free from active devices therein. Yu is silent to an encapsulant that encapsulating the first substrate block therein. However, Tsai discloses an encapsulant 48 encapsulating a first substrate block such that the conductive path 32 in the first substrate block extends all the way from a top surface level to a bottom surface level of the encapsulant (see paragraph [0023] and fig. 26).
Thus, contrary to Applicant’s contention that one of ordinary skill in the art will not be motivated to combine the teaching of Tsai and Yu since one of ordinary skill in the art can simply make the asserted first substrate block larger without needing extra effector and cost of forming fan-out package form a smaller first substrate block, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Tsai into the structure of Yu because when the encapsulant of Tsai is incorporated into the structure of Yu, the encapsulant would encapsulating the first substrate block and the conductive path would be extending from the top surface level to the bottom surface level of the encapsulant and the encapsulant protecting the first substrate block from the outside environment.
Applicant’s amendment and argument with respect to independent claim 12 has been fully considered and is persuasive, thus claims 12-17 have been indicated as allowable as presented in paragraphs No. 8 and 9 above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHIEM D NGUYEN whose telephone number is (571)272-1865. The examiner can normally be reached Monday-Friday 8:00 AM - 6:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/KHIEM D NGUYEN/Primary Examiner, Art Unit 2892