DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Le et al. (20210074702) in view of Kim (20240306383).
Regarding Claim 1, in Figs. 3 and 4, Le et al. discloses semiconductor structure, comprising: an interconnect structure 294 over a substrate 210; and a transistor 102/104 embedded in the interconnect structure and comprising: at least one gate layer 202g/204g; a gate dielectric layer 202g/204g extending along the at least one gate layer; a channel layer (2DEG for example) extending along the gate dielectric layer; a heterostructure interposed between the gate dielectric layer and the channel layer. Le et al. fails to disclose the required the heterostructure comprising a two-dimensional electron gas (2DEG) region which acts as a part of a channel of the transistor; and source/drain (S/D) vias connected to the channel layer in required configuration. However, Kim discloses a semiconductor device where in paragraphs 0068, 0069, 0071, 0073-0076, 0109,0110, 0113 and 0153 the required heterostructure is disclosed.
It would have been obvious to one of having ordinary skill in the art before the effective filing date of the claimed invention to have the required heterostructure in Le et al. as taught by Kim in order to enhance the channel with oxygen vacancy.
Regarding Claim 2 in paragraphs 0068, 0069, 0071, 0073-0076, 0109,0110, 0113 and 0153 of Kim, the heterostructure comprises a first metal oxide material overlying the gate dielectric layer, a second metal oxide material underlying the channel layer and different from the first metal oxide material, and the 2DEG region located at an interface between the first and second metal oxide materials.
Regarding Claim 3, in paragraphs 0068, 0069, 0071, 0073-0076, 0109,0110, 0113 and 0153 of Kim, a material of the channel layer is different from the first and second metal oxide materials of the heterostructure.
Regarding Claim 4, in paragraphs 0068, 0069, 0071, 0073-0076, 0109,0110, 0113 and 0153 of Kim, free electrons in the heterostructure move in a direction parallel to an interface of the heterostructure and are geometrically confined in a thickness direction of the heterostructure.
Regarding Claim 5, in paragraphs 0068, 0069, 0071, 0073-0076, 0109,0110, 0113 and 0153 of Kim, free electrons in the channel layer move in three dimensions.
Regarding Claim 6, in Figs. 3 and 4 of Let et al., bottom surfaces of the S/D vias 202s/202d/204s/204d are between a top surface of the channel layer and a top surface of the heterostructure.
Regarding Claim 7, in Figs. 3 and 4 of Le et al, sidewalls of the channel layer and the heterostructure are substantially coplanar.
Regarding Claim 8, in Figs. 3 and 4 of Le et al., a thickness of the channel layer is greater than that of the heterostructure.
Regarding Claim 9, in Figs. 3 and 4 of Le et al, an effective thickness of the 2DEG region is in a range of 80 percent and 100 percent of an overall thickness of the heterostructure.
Regarding Claim 10, in Figs 3 and 4 of Le et al, the at least one gate layer comprises a plurality of gate layers, the gate layers and isolation layers are alternately stacked to form a stacking structure, the gate dielectric layer covering a sidewall of the stacking structure, and the S/D vias separately stand aside the stacking structure and are in lateral contact with the channel layer.
Regarding Claim 11, in Figs. 3 and 4 and paragraph 0050 of Le et al, a capping layer overlying the channel layer, wherein the S/D vias penetrate through the capping layer and extend into the channel layer.
Regarding Claim 12, in Figs. 3 and 4, the interconnect structure 294 comprises a dielectric layer and a conductive pattern embedded in the dielectric layer, and the transistor is embedded in the dielectric layer and electrically coupled to the conductive pattern.
Regarding Claim 13, in Figs. 3 and 4 of Le et al, it is disclosed semiconductor structure, comprising: a transistor 102/104 embedded in an interconnect structure 294 over a substrate 210, the transistor comprising: a gate electrode 202g/204g; a gate dielectric layer 202g/204g overlying the gate electrode; a channel layer (2DEG for example) over the gate dielectric layer; a two-dimensional electron gas (2DEG) region interposed between the channel layer and the gate dielectric layer, wherein free electrons in the 2DEG region move in two dimensions and are confined in a thickness direction of the 2DEG region; and S/D electrodes connected to the channel layer. Le et al. fails to disclose the limitation where the 2DEG region acting as a part of a channel of the transistor. However, Kim discloses a semiconductor device where in paragraphs 0068, 0069, 0071, 0073-0076, 0109,0110, 0113 and 0153 the required 2DEG/channel structure is disclosed.
It would have been obvious to one of having ordinary skill in the art before the effective filing date of the claimed invention to have the required 2DEG/channel structure in Le et al. as taught by Kim in order to enhance the channel with oxygen vacancy.
Regarding Claim 14, in paragraphs 0068, 0069, 0071, 0073-0076, 0109,0110, 0113 and 0153 of Kim, transistor further comprises: a heterostructure comprising an upper metal oxide material underlying the channel layer and a lower metal oxide material overlying the gate dielectric layer, wherein the 2DEG region is an intermixing region between the upper and lower metal oxide materials.
Regarding Claim 15, in Figs. 3 and 4, the 2DEG region is a short-range order layer.
Regarding Claim 16, in Figs. 2 and 4, the transistor is a high electron mobility transistor.
Regarding Claim 17, in Figs. 3-5, Le et al. disc manufacturing method of a semiconductor structure, comprising: forming a transistor 104/104 in an interconnect structure 296 over a substrate 210 comprising: forming a gate dielectric layer 202g/204g on a gate layer; forming, wherein the heterostructure comprises; forming a channel (2DEG for example; and forming S/D vias on the channel layer. Le et al. fails to disclose the limitation where the heterostructure and 2DEG region acting as a part of a channel of the transistor. However, Kim discloses a semiconductor device where in paragraphs 0068, 0069, 0071, 0073-0076, 0109,0110, 0113 and 0153 the required 2DEG/channel structure is disclosed.
It would have been obvious to one of having ordinary skill in the art before the effective filing date of the claimed invention to have the required heterostructure 2DEG/channel structure in Le et al. as taught by Kim in order to enhance the channel with oxygen vacancy.
Regarding Claim 18, 0068, 0069, 0071, 0073-0076, 0109,0110, 0113 and 0153 of Kim, forming the heterostructure comprises: forming a first metal oxide material on the gate dielectric layer; forming a second metal oxide material on the first metal oxide material; performing a thermal treatment on the first and second metal oxide materials, wherein after the thermal treatment, the 2DEG region is formed at a heterojunction of the first and second metal oxide materials.
Regarding Claim 19, in paragraphs 0023, 0047 and 0057 of Le et al, performing the thermal treatment comprises: annealing the first and second metal oxide materials at a temperature below about 400°C.
Regarding Claim 20, in Kim, materials and forming processes of the heterostructure are compatible with a back-end-of-line (BEOL) process.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FAZLI ERDEM whose telephone number is (571)272-1914. The examiner can normally be reached M-F, 8am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at 571-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/FAZLI ERDEM/Primary Examiner, Art Unit 2812 6/27/2026
Prosecution Insights