DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 9-14, and 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ryan et al (2019/0019726, hereafter Ryan).
Regarding claim 1, Ryan discloses an interconnection structure, comprising: a first conductive line (215 right, Fig. 2H, par. 0015) extending in a first direction and embedded in a first insulation layer (205, Fig. 2H, par. 0013); a second conductive line (260, Fig. 2H, par. 0022) extending above the first conductive line in a second direction, wherein the second direction crosses the first direction; a second insulation layer (210, Fig. 2H, par. 0015) disposed between the first conductive line and the second conductive line; and a dielectric pattern (240, Fig. 2H, par. 0019) disposed in a portion of the second insulation layer where the first conductive line and the second conductive line cross each other in a top view.
Regarding claim 2, Ryan discloses an interconnection structure wherein a material of the dielectric pattern (240) is different from a material of the second insulation layer (210) (par. 0015, 0019).
Regarding claim 3, Ryan discloses an interconnection structure wherein a dielectric constant of the dielectric pattern (240) is greater than a dielectric constant of the second insulation layer (210) (par. 0015, 0019). (par. 0019 states 240 can be formed of any dielectric or oxide material, which includes higher dielectric constants, such as aluminum-oxide; par. 0015 states 210 can be SiN, SiCNH, or other oxide materials which have lower dielectric constants.)
Regarding claim 4, Ryan discloses an interconnection structure wherein a dielectric constant of the dielectric pattern (240) is greater than a dielectric constant of silicon oxide (par. 0019), and a dielectric constant of the second insulation layer (210) is less than the dielectric constant of the silicon oxide (par. 0015). (par. 0019 states 240 can be formed of any dielectric or oxide material, which includes higher dielectric constants, such as aluminum-oxide; par. 0015 states 210 can be any oxide materials which includes lower dielectric constants, such as fluorine or carbon doped oxides.)
Regarding claim 9, Ryan discloses an interconnection structure further comprising: a third conductive line (215 left, Fig. 2H) embedded in the first insulation layer (205, Fig. 2H), electrically connected to the second conductive line (260, Fig. 2H, par. 0023), and electrically isolated from the first conductive line (215 right, Fig. 2H), wherein the dielectric pattern (240, Fig. 2F) comprises an opening (230, Fig. 2G, par. 0021), and a conductive via (260 bottom, Fig. 2H) electrically connecting the third conductive line to the second conductive line is disposed in the opening.
Regarding claim 10, Ryan discloses an interconnection structure wherein a top surface of the dielectric pattern (240, Fig. 2H) is in direct contact with the second conductive line (260, Fig. 2H, par. 0022).
Regarding claim 11, Ryan discloses an interconnection structure wherein the dielectric pattern (240, Fig. 2H) comprises an island pattern disposed at a position where the first conductive line (225 right, Fig. 2H) and the second conductive line (260, Fig. 2H) overlap each other.
Regarding claim 12, Ryan discloses an interconnection structure wherein the dielectric pattern (240, Fig. 2H) comprises a rectangular pattern elongated in the second direction (Fig. 2H).
Regarding claim 13, Ryan discloses a method for forming an interconnection structure, comprising: forming a first conductive line (215 right, Fig. 2H, par. 0015) extending in a first direction and embedded in a first insulation layer (205, Fig. 2H, par. 0013); forming a dielectric pattern (240, Fig. 2H, par. 0019) on the first insulation layer; forming a second insulation layer (210, Fig. 2H, par. 0015) covering the dielectric pattern on the first insulation layer; and forming a second conductive line (260, Fig. 2H, par. 0022) extending in a second direction on the second insulation layer, wherein the second direction crosses the first direction, wherein the dielectric pattern is formed in a portion of the second insulation layer where the first conductive line and the second conductive line cross each other in a top view (Fig. 2H).
Regarding claim 14, Ryan discloses a method wherein a dielectric constant of the dielectric pattern (240) is greater than a dielectric constant of the second insulation layer (210) (par. 0015, 0019). (par. 0019 states 240 can be formed of any dielectric or oxide material, which includes higher dielectric constants, such as aluminum-oxide; par. 0015 states 210 can be SiN, SiCNH, or other oxide materials which have lower dielectric constants.)
Regarding claim 18, Ryan discloses a method further comprising: forming a third conductive line (215 left, Fig. 2H) embedded in the first insulation layer (205, Fig. 2H), wherein the third conductive line is electrically connected to the second conductive line (260, Fig. 2H, par. 0023) and electrically isolated from the first conductive line (215 right, Fig. 2H), wherein the dielectric pattern (240, Fig. 2F) comprises an opening (230, Fig. 2G, par. 0021), and a conductive via (260 bottom, Fig. 2H) electrically connecting the third conductive line to the second conductive line is disposed in the opening.
Regarding claim 19, Ryan discloses a method wherein a step of forming the second conductive line comprises: forming a trench (230, Fig. 2G) exposing a top surface of the dielectric pattern (240, Fig. 2F) in the second insulation layer (210, Fig. 2F, 2G); forming a via hole (230, Fig. 2G) in the opening of the dielectric pattern in the second insulation layer; and filling a conductive material (260, Fig. 2H) in the trench and the via hole to form the second conductive line and the conductive via (260 bottom, Fig. 2H).
Regarding claim 20, Ryan discloses a method wherein the dielectric pattern (240, Fig. 2H) is isolated from the second conductive line (260 bottom, Fig. 2H) by the second insulation layer (210, Fig. 2H).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Ryan in view of Chiu (2022/0199769, hereafter Chiu).
Regarding claim 5, Ryan is discussed above. Ryan fails to disclose an interconnection structure wherein a voltage applied to the first conductive line is different from a voltage applied to the second conductive line.
However, Chiu teaches an interconnection structure wherein a voltage applied to the first conductive line is different from a voltage applied to the second conductive line (par. 0116).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Ryan with Chiu by applying different voltages to different conductive lines so that the programmable units may be programmed one at a time or multiple programmable units may be programmed simultaneously.
Regarding claim 15, Ryan fails to disclose a method wherein a voltage applied to the first conductive line is different from a voltage applied to the second conductive line.
However, Chiu teaches a method wherein a voltage applied to the first conductive line is different from a voltage applied to the second conductive line (par. 0116).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Ryan with Chiu by applying different voltages to different conductive lines so that the programmable units may be programmed one at a time or multiple programmable units may be programmed simultaneously.
Claims 6-8, 16, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Ryan in view of Anderson et al. (2017/0186682, hereafter Anderson).
Regarding claim 6, Ryan is discussed above. Ryan fails to disclose an interconnection structure further comprising: an etch stop layer disposed between the first insulation layer and the second insulation layer; and a cap layer disposed between the etch stop layer and the second insulation layer, wherein the cap layer covers a side surface of the dielectric pattern.
However, Anderson teaches an interconnection structure further comprising: an etch stop layer (142, Fig. 6, par. 0020) disposed between the first insulation layer (140, Fig. 6) and the second insulation layer (106, Fig. 6); and a cap layer (124, Fig. 6, par. 0016) disposed between the etch stop layer and the second insulation layer, wherein the cap layer covers a side surface of the dielectric pattern (120, Fig. 6, par. 0023).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Ryan with Anderson by providing an etch stop layer and capping layer between the insulating layers in order to control via etching depth and prevent electromigration or diffusion of metal from conductive lines into insulation.
Regarding claim 7, Ryan fails to disclose an interconnection structure wherein the cap layer covers a top surface of the dielectric pattern.
However, Anderson teaches an interconnection structure wherein the cap layer (124, Fig. 6) covers a top surface of the dielectric pattern (120, Fig. 6).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Ryan with Anderson by providing a cap layer that covers the top surface of the dielectric pattern in order to act as diffusion barrier, improve interfacial adhesion, and protect from damage during etching or polishing.
Regarding claim 8, Ryan fails to disclose an interconnection structure wherein a thickness of the cap layer is less than a thickness of the dielectric pattern.
However, Anderson teaches an interconnection structure wherein a thickness of the cap layer (124, Fig. 6) is less than a thickness of the dielectric pattern (120, Fig. 6).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Ryan with Anderson by providing a cap layer with a thickness less than the dielectric pattern in order to minimize parasitic capacitance while ensuring effective adhesion and protection.
Regarding claim 16, Ryan fails to disclose a method further comprising: forming an etch stop layer between the first insulation layer and the second insulation layer; and forming a cap layer between the etch stop layer and the second insulation layer, wherein the cap layer covers a side surface of the dielectric pattern.
However, Anderson teaches a method further comprising: forming an etch stop layer (142, Fig. 6, par. 0020) between the first insulation layer (140, Fig. 6) and the second insulation layer (106, Fig. 6); and forming a cap layer (124, Fig. 6, par. 0016) between the etch stop layer and the second insulation layer, wherein the cap layer covers a side surface of the dielectric pattern (120, Fig. 6, par. 0023).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Ryan with Anderson by providing an etch stop layer and capping layer between the insulating layers in order to control via etching depth and prevent electromigration or diffusion of metal from conductive lines into insulation.
Regarding claim 17, Ryan fails to disclose a method wherein the cap layer is formed to cover a top surface of the dielectric pattern.
However, Anderson teaches a method wherein the cap layer (124, Fig. 6) is formed to cover a top surface of the dielectric pattern (120, Fig. 6).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Ryan with Anderson by providing a cap layer that covers the top surface of the dielectric pattern in order to act as diffusion barrier, improve interfacial adhesion, and protect from damage during etching or polishing.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHARLES M BRECHT whose telephone number is (571)272-9634. The examiner can normally be reached Mon-Fri: 7:30am - 5pm.
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/C.M.B./ Examiner, Art Unit 2817
/MARLON T FLETCHER/ Supervisory Primary Examiner, Art Unit 2817
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