Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5, 7-12, and 14 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Tsai et al. (US Pat. Pub. 2018/0315652).
Regarding claim 1, Tsai teaches an integrated chip comprising:
a source/drain region along a substrate [fig. 18, 42, paragraph [0020] teaches they are source/drain regions];
a contact layer over the source/drain region [fig. 18, 84 above 42];
a first spacer along a first sidewall of the contact layer [fig. 18, 38 on the left side of 84];
a second spacer along a second sidewall of the contact layer [fig. 18, 38 on the right side of 84];
a dielectric layer over the contact layer and between the first spacer and the second spacer [fig. 18, 90 is located above 84 and extends to an area between 38 on either side of 84]; and
a liner layer between the dielectric layer and the first spacer [fig. 18, 88].
Regarding claim 2, Tsai discloses the integrated chip of claim 1, further comprising: a conductive via over the contact layer and between the first spacer and the second spacer [fig. 18, 96 above 84].
Regarding claim 3, Tsai teaches the integrated chip of claim 2, wherein the conductive via extends through the dielectric layer and the liner layer to an upper surface of the contact layer [fig. 18, 96 extends through 90 and 88 to an upper surface of 84].
Regarding claim 4, Tsai discloses the integrated chip of claim 2, wherein the liner layer is between the conductive via and the first spacer [fig. 18, liner 88 is between at least a portion of 96 and spacer 38].
Regarding claim 5, Tsai teaches the integrated chip of claim 2, wherein the liner is on a sidewall of the conductive via [fig. 18, 88 is present on a sidewall of 96].
Regarding claim 7, Tsai discloses the integrated chip of claim 1, wherein the liner layer is directly between a lower surface of the dielectric layer and an upper surface of the first spacer [fig. 18, 88 is present between a lower surface of 90 and a n upper surface of 38].
Regarding claim 8, Tsai teaches the integrated chip of claim 1, wherein the liner layer is directly between a lower surface of the dielectric layer and an upper surface of the contact layer [fig. 18, 88 is present between a lower surface of 90 and an upper surface of 84].
Regarding claim 9, Tsai discloses an integrated chip comprising:
a source/drain region arranged along a substrate [fig. 18, 42, paragraph [0020] teaches they are source/drain regions];
a first spacer and a second spacer over the substrate [fig. 18, 38 on either side of 84, left side is first, right side is second];
a contact layer over the source/drain region and between the first spacer and the second spacer [fig. 18, 84 above 42 between elements 38];
a hard mask over the contact layer and between the first spacer and the second spacer [fig. 18, 90 is above 84 and extends between elements 38];
a via over the contact layer and between the first spacer and the second spacer [fig. 18, 96]; and
a liner layer between the via and the first spacer [fig. 18, liner 88 is between at least a portion of 96 and spacer 38].
Regarding claim 10, Tsai teaches the integrated chip of claim 9, wherein the liner layer is directly over the first spacer [fig. 18, 88 is directly above 38 on the left side of 84].
Regarding claim 11, Tsai discloses the integrated chip of claim 9, wherein the liner layer is directly between the first spacer and the second spacer [fig. 18, 88 extends to the region between elements 38, as best understood by the examiner this is directly between].
Regarding claim 12, Tsai teaches the integrated chip of claim 11, wherein the liner layer is directly over the contact layer [fig. 18, 88 is directly above 84].
Regarding claim 14, Tsai discloses the integrated chip of claim 9, wherein the liner layer is directly between the via and the second spacer [fig. 18, 88 is between a portion of 96 and spacers 38].
Allowable Subject Matter
Claim 16-20 are allowed.
Claims 6, 13 and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 16, the prior art fails to disclose or suggest the device as claimed. Specifically, the prior art fails to teach a dielectric liner extending along a sidewall of the first dielectric spacer, a sidewall of the second dielectric spacer and an upper surface of the contact layer, a dielectric hard mask extending along a first sidewall of the dielectric liner layer, a second sidewall of the dielectric liner layer and an upper surface of the dielectric liner layer and a conducive via extending through the dielectric hard mask and the upper surface of the dielectric liner to the upper surface of the conductive contact layer.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN M PARKER whose telephone number is (571)272-8794. The examiner can normally be reached M-F 7:30am - 3:30pm.
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/JOHN M PARKER/Primary Examiner, Art Unit 2899
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