DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 6-8, 14, 16 and 19 are rejected under 35 U.S.C. 102(a)(1)as being anticipated by Mitani (US 20140183636 A1).
Regarding Claim 1, Mitani discloses a method comprising:
implanting a substrate 2 with a dopant 6 to form an implanted layer 7 in the substrate 2 (Fig. 5(b): 2, 6, 7, paragraph 0140, 0143);
thinning the substrate 2 (Fig. 5 (e): 2, paragraph 0153);
and heating the substrate 2 to split the substrate 2 at the implanted layer 7, wherein the substrate 2 is split into a first portion 11 and a second portion 2’ (Fig. 5(e): 2, 2’, 11, 7, paragraph 0143, 0150).
Regarding Claim 2, Mitani teaches the method of claim 1, wherein thinning the substrate 2 is done by etching, grinding, or chemical mechanical polishing (CMP) (paragraph 0153).
Regarding Claim 6, Mitani teaches the method of claim 1, wherein the substrate 2 has a single crystalline structure (paragraph 0141).
Regarding Claim 7, Mitani teaches the method of claim 6, wherein the substrate 2comprises a dielectric material (i.e., SiO2, see paragraph 0141).
Regarding Claim 8, Mitani teaches the method of claim 6, wherein the substrate 10 comprises a semiconductor material (i.e., silicon, see paragraph 0141).
Regarding Claim 14, Mitani et al. discloses a method comprising:
implanting a substrate 2 with a dopant 6 to form an implanted layer 7 in the substrate 2 (Fig. 5(b): 2, 6, 7, paragraph 0140, 0143);
wherein the implanted layer 7 is spaced apart from a first surface (bottom surface of 2 in the orientation of Fig. 5c) and a second surface (top surface of 2 in the orientation of Fig. 5c) of the substrate 2 (see Fig. 5(c): 2, 7, paragraph 0143),
and wherein the implanted layer 7 is closer to the first surface (bottom surface of 2 in the orientation of Fig. 5c) of the substrate 2 than the second surface (top surface of 2 in the orientation of Fig. 5c) of the substrate 2 (see Fig. 5(c): 2, 7, paragraph 0143);
bonding the substrate 2 to a wafer 13 (Fig. 5(d): 2, 13, paragraph 0149),
wherein the first surface (bottom surface) of the substrate 2 faces the wafer 13 (see Fig. 5(d): 2, 13);
thinning the substrate 2 at the second surface (top surface) (Fig. 5 (e): 2, paragraph 0153);
and heating the substrate 2 to split the substrate 2 at the implanted layer 7, wherein the substrate 2 is split into a first portion 11 and a second portion 2’ (Fig. 5(e): 2, 2’, 11, 7, paragraph 0143, 0150).
Regarding Claim 16, Mitani teaches the method of claim 14, wherein heating the substrate 2 is performed at a temperature higher than 200˚C (paragraph 0152).
Note that the heating temperature is higher than 500 ˚C and less than 700 ˚C (paragraph 0152), which overlaps the claimed range. According to MPEP § 2144.05 (I), “In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists”. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Regarding Claim 19, Mitani et al. teaches the method of claim 14, wherein the substrate 10 comprises silicon, gallium arsenide, or indium phosphide (see paragraph 0141).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection note: Italicized claim limitations are limitations not explicitly disclosed in the primary
reference but disclosed in the secondary reference(s).
Claims 3-5 are rejected under 35 U.S.C. 103 as being unpatentable over Mitani (US 20140183636 A1), as applied to Claim 1 above, further in view of Tai et al. (US 20190036009 A1).
Regarding Claim 3, the Mitani teaches the method of claim 1, further comprising bonding the substrate 2 to a wafer 13 by bonding a first bonding layer on the substrate 2 to a second bonding layer on the wafer 13 before thinning the substrate 2 (Fig. 5(d): 2, 13, paragraph 0149).
While Mitani fails to teach a first bonding layer and a second bonding layer, Tai et al. teaches bonding the substrate 1 to a wafer 6 by bonding a first bonding layer 4A on the substrate 1 to a second bonding layer 4B on the wafer 6 (Fig. 9(a): 1, 6, 4A, 4B, paragraph 0071).
Therefore, it would have been obvious to a person of ordinary sill in the art before the effective filing date of the claimed invention, to have combined the teachings of Mitani and Tai et al. in order to include a step of bonding the substrate to a wafer by bonding a first bonding layer on the substrate to a second bonding layer on the wafer. Doing so would improve the bond strength between the substrate and the wafer.
Regarding Claim 4, Mitani et al. teaches the method of claim 3, wherein the first portion 11 of the substrate 2 remains bonded to the wafer 13 after heating the substrate 2, and wherein a thickness of the first portion 11 of the substrate 2 is smaller than 1 µm (Fig. 5(e): 11, 13, 2, paragraph 0208).
Note that paragraph 0208 states the thickness is about 0.1 µm, which is smaller than 1 µm.
Regarding Claim 5 Mitani fails to explicitly teach the method of claim 3, wherein the substrate has a higher coefficient of thermal expansion (CTE) than the wafer.
However, Tai et al. teaches wherein the substrate 10 has a higher coefficient of thermal expansion (CTE) than the wafer 20 (paragraph 0087).
Therefore, it would have been obvious to a person of ordinary sill in the art before the effective filing date of the claimed invention, to have combined the teachings of Mitani and Tai et al. in order to have the substrate have a higher coefficient of thermal expansion (CTE) than the wafer. Doing so would prevent thermal-stress induced damage to the wafer.
Claims 15 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Mitani (US 20140183636 A1), as applied to Claim 14 above, further in view of Tai et al. (US 20190036009 A1).
Regarding Claim 15 Mitani fails to explicitly teach the method of claim 14, wherein the substrate has a higher coefficient of thermal expansion (CTE) than the wafer.
However, Tai et al. teaches a method of bounding a substrate 1 to a wafer 6, wherein the substrate 1 has a higher coefficient of thermal expansion (CTE) than the wafer 6 (paragraph 0087).
Therefore, it would have been obvious to a person of ordinary sill in the art before the effective filing date of the claimed invention, to have combined the teachings of Mitani and Tai et al. in order to have the substrate have a higher coefficient of thermal expansion (CTE) than the wafer. Doing so would prevent thermal-stress induced damage to the wafer.
Regarding Claim 20, Mitani fails to teach the method of claim 14, wherein the substrate comprises lithium niobate or lithium tantalate.
However, Tai et al. teaches a method of bounding a substrate 1 to a wafer 6, wherein the substrate 1 comprises lithium niobate or lithium tantalate (paragraph 0086).
Therefore, it would have been obvious to a person of ordinary sill in the art before the effective filing date of the claimed invention, to have combined the teachings of Mitani and Tai et al. in order to have the substrate comprises lithium niobate or lithium tantalate. Doing so would enable the use of piezoelectric materials as substrates, as recognized by Tai et al. (paragraph 0086), and suitable for photonic and Rf device applicant.
Claims 9-13, 17 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Mitani (US 20140183636 A1).
Regarding Claim 9, Mitani discloses a method comprising:
implanting a substrate 2 with a dopant 6 to form an implanted layer 7 in the substrate 2 (Fig. 5(b): 2, 6, 7, paragraph 0140, 0143);
bonding the substrate 2 to a wafer 13 with integrated circuit devices (Fig. 5(d): 2, 13, paragraph 0149);
thinning the substrate 2 (Fig. 5 (e): 2, paragraph 0153);
and heating the substrate 2 to split the substrate 2 at the implanted layer 7, wherein the substrate 2 is split into a first portion 11 and a second portion 2’, and wherein the first portion 11 of the substrate 2 remains bonded to the wafer 13 after heating the substrate 2 (Fig. 5(e): 2, 2’, 11, 7, paragraph 0143, 0150).
In a different embodiment, Mitani teaches a wafer 300 with integrated circuit devices 310 (Fig. 9: 300, 310, paragraph 0262);
Therefore, it would have been obvious to a person of ordinary sill in the art before the effective filing date of the claimed invention, to have combined the different embodiments of Mitani in order to have the wafer with integrated circuit devices. Doing so would allow the substrate to be integrated with preprocessed functional circuitry, thereby minimizing manufacturing time, cost and process complexity.
Regarding Claim 10, Mitani teaches the method of claim 9, wherein the first portion 11 of the substrate 2 comprises an implanted region (top surface of 11) and an un-implanted region (area other than the top surface of 11) (see Fig. 5e).
Regarding Claim 11, Mitani teaches the method of claim 9, wherein the dopant is hydrogen or helium (paragraph 0143).
Regarding Claim 12, Mitani teaches the method of claim 9, further comprising planarizing the first portion 11 of the substrate 2 after heating the substrate 2 (paragraph 0153).
Note that paragraph 0153 states the portion 11 is polished.
Regarding Claim 13, Mitani teaches the method of claim 12, further comprising, patterning the first portion of the substrate to form photonic devices after the first portion of the substrate is planarized (Fig. 10 shows the formation of a display device, see also paragraph 0271).
Regarding Claim 17, Mitani teaches the method of claim 14, wherein the substrate has a thickness less than 100 µm after thinning the substrate (see paragraph 0097).
Note that in a different embodiment, the substrate has a thickness of about 635 µm (see paragraph 0121). A person of ordinary skill in the art would have recognized that after thinning the substrate, the thickness will be less than 635 µm, which overlaps the claimed range. According to MPEP § 2144.05 (I), “In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists”. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Regarding Claim 18, Mitani et al. fails to explicitly teach the method of claim 14, wherein the substrate 2 is bonded to the wafer 3 by dielectric-to-dielectric bonding.
However, Mitani teaches the substrate 2 has a thermal oxide layer 12’ on the bonding surface (see Fig. 5C, paragraph 0141), and the wafer 13 is silicon (paragraph 0146) which inherently forms a native silicon oxide on its surface. Therefore, the mechanism of bonding is governed by interactions between oxide surfaces which are dielectric layers, resulting in the substrate bonded to the wafer by dielectric-to-dielectric bonding.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Couillard et al. (US 20100213582 A9) teaches a method of bonding a substrate to a wafer
Yonehara (US 20050124137 A1) teaches a method of bonding a substrate to a wafer
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAMNA F IQBAL whose telephone number is 571-272-1587. The examiner can normally be reached M-F: 8.30 am - 5.30 pm EST.
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/HAMNA FATHIMA IQBAL/Examiner, Art Unit 2817 06/12/2026
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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