Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of claims 1-10 in the reply filed on 9/4/2026 is acknowledged. The traversal is on the ground(s) that there would be no undue burden on the Examiner to consider all claims in the single application. This is not found persuasive because the invention of claims 11-20 is of a different statu.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 6 recites the limitation "first gate dielectric electrical layer" in lines 10-11. There is insufficient antecedent basis for this limitation in the claim. Examiner interprets this to refer to the first gate dielectric layer, and the claim has been examined accordingly.
The term “close to” in claim 7 is a relative term which renders the claim indefinite. The term “close to” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. The limitation “wherein a sidewall of the interlayer dielectric layer is located on the first dielectric layer close to the first electrode” is therefore indefinite.
The term “close to” in claim 8 is a relative term which renders the claim indefinite. The term “close to” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. The limitation "source regions and pick-up doped regions located on the well region in the second region and close to a top surface of the epitaxial layer" is therefore indefinite.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsieh '576 (US 20130020576 A1) in view of Yedinak (US 20090008709 A1).
Regarding claim 1, Hsieh '576 discloses a semiconductor device (Fig. 7), comprising: a substrate (N+ substrate, labeled 105 in Fig. 2A), wherein the substrate has a first region (501) and a first conductivity type ("N+ substrate 105"); an epitaxial layer (N epitaxial layer, labeled 104 in Fig. 2A)
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disposed on a top surface of the substrate, wherein the epitaxial layer has the first conductivity type (Shown); a first electrode (522; see attached figure) disposed in the epitaxial layer in the first region and extending in a first direction (Y direction); a separated conductive structure (see attached figure) disposed in the epitaxial layer in the first region (Shown), wherein the separated conductive structure comprises: a first conductive feature and a second conductive feature (see attached figure) separated from each other and located on opposite sidewalls of the first electrode (Shown); and a source metal layer (517) disposed on the epitaxial layer in the first region, wherein the source metal layer covers the first conductive feature, the second conductive feature, and the first electrode, and the source metal layer is electrically connected to the first conductive feature, the second conductive feature, and the first electrode (Shown). On the other hand, Hsieh ‘576 does not disclose wherein the substrate is a silicon carbide substrate.
On the other hand, Yedinak discloses wherein the substrate is a silicon carbide substrate (Para. 162 "the power devices described herein are fabricated in a substrate made of wide-bandgap material, including for example, silicon carbide"). It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Hsieh '576 according to the teachings of Yedinak such that the substrate would have been a silicon carbide substrate, in order to employ the well-known characteristics of silicon carbide, such as high E field capabilities and good thermal performance, especially in comparison to silicon.
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Regarding claim 2, Hsieh '576 discloses further comprising: a contact barrier layer (contact insulating layer 118, not labeled but understood to be the layer in the attached figure) disposed on the epitaxial layer in the first region, wherein the contact barrier layer is in direct contact with the source metal layer and at least one of the first electrode, the first conductive feature and the second conductive feature (Shown).
Claim(s) 3-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsieh '576 (US 20130020576 A1) in view of Yedinak (US 20090008709 A1) above, and further in view of Hsieh '760 (US 20130168760 A1).
Regarding claim 3, Hsieh ‘576 discloses the substrate having a second region (Fig. 5, Trench MOSFET region). However, Hsieh ‘576 does not disclose the semiconductor device further comprises: a well region located in the epitaxial layer wherein the well region has a second conductivity type a second electrode disposed in the epitaxial layer in the second region and extending along the first direction a split gate structure disposed in the epitaxial layer in the second region wherein the split gate structure comprises: a first gate and a second gate separated from each other and located on opposite sidewalls of the second electrode an interlayer dielectric layer disposed on the epitaxial layer in the second region and source contacts passing through the interlayer dielectric layer in the second region and extending into the second electrode and the well region wherein the source metal layer covers the source contacts and is electrically connected to the source contacts.
On the other hand, Hsieh '760 discloses the semiconductor device further comprises: a well region (Fig. 2B, labeled p body region 210 in Fig. 2A) located in the epitaxial layer (N- layer, labeled 202 in Fig. 2A) wherein the well region has a second conductivity type (Para. 8 "a body region of the second conductivity type"); a second electrode (207) disposed in the epitaxial layer in the second region (Shown) and extending along the first direction (Y direction); a split gate structure (Instances of 206 on either side of 207) disposed in the epitaxial layer in the second region (Shown), wherein the split gate structure comprises: a first gate (Leftmost G) and a second gate (rightmost G) separated from each other and located on opposite sidewalls of the second electrode (Shown); an interlayer dielectric layer (contact interlayer 214; para. 40 "In FIG. 7F, another oxide layer is deposited onto the top surface of the epitaxial layer 701 to serve as a contact interlayer 715") disposed on the epitaxial layer in the second region (Shown); and source contacts (comprises 223-1 and 213) passing through the interlayer dielectric layer in the second region (Shown) and extending into the second electrode (223-1 is shown extending into electrode 207) and the well region (213 is shown extending into well region), wherein the source metal layer covers the source contacts (215), and is electrically connected to the source contacts (215 is shown connecting to both 223-1 and 213). It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Hsieh '576 in view of Yedinak according to the teachings of Hsieh '760 such that the structure of Hsieh ‘760 comprising a well region, a second electrode, a split gate structure, an interlayer dielectric layer, and source contacts would be integrated into the second region of Hsieh ‘576, in order to achieve higher speed and efficiency in the device (Hsieh ‘576 para. 2 “a Schottky rectifier is externally added in parallel with a MOSFET device to prevent a parasitic P/N body diode in the MOSFET from turning on in order to achieve higher speed and efficiency”).
Regarding claim 4, Hsieh '760 discloses wherein the first electrode is exposed from the interlayer dielectric layer (Fig. 7 shows top portion of first electrode 52 exposed from interlayer dielectric layer).
Regarding claim 5, Hsieh '760 discloses wherein at least one of the first conductive feature and the second conductive feature is exposed from the interlayer dielectric layer (Fig. 7 shows first and second conductive features 522 exposed from the interlayer dielectric).
Regarding claim 6, Hsieh ‘576 disclose further comprising: a first dielectric layer (Fig. 7, first type gate oxide 512) disposed in the epitaxial layer in the first region (Shown) and surrounding the first conductive feature and the second conductive feature (Shown), wherein the first electrode, the first conductive feature and the second conductive feature are exposed from a top surface of the first dielectric layer (Shown). However, Hsieh ‘576 does not disclose wherein the split gate structure further comprises: a first gate dielectric layer disposed in the epitaxial layer and surrounding the first gate and the second gate, wherein the interlayer dielectric layer covers the first gate dielectric layer.
On the other hand, Hsieh ‘760 discloses wherein the split gate structure further comprises a first gate dielectric layer (Fig. 2B, labeled 240 in Fig. 2A) disposed in the epitaxial region and surrounding the first gate and the second gate, wherein the interlayer dielectric layer covers the first gate dielectric layer. It would have been obvious to one of ordinary skill in the art before the time of effective filing to modify Hsieh ‘576 in view of Yedinak according to the teachings of Hsieh ‘760 such that the split gate structure would comprise a first gate dielectric layer disposed in the epitaxial layer in the second region and surrounding the first gate and the second gate, and wherein the interlayer dielectric layer would cover the first gate dielectric layer, in order to improve the reliability of the device be electrically isolating conductive elements such as the first and second gates from other conductive elements.
Regarding claim 7, Hsieh ‘576 discloses wherein a sidewall of the interlayer dielectric layer is located on the first dielectric layer close to the first electrode (see attached figure).
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Regarding claim 8, Hsieh ‘760 discloses source regions (Fig. 2B, N+ region, labeled 211 in Fig. 2A) and pick-up doped regions (P+ region, labeled 216 in Fig. 2A) located on the well region (shown) and close to a top surface of the epitaxial layer (shown), wherein the source regions and the pick-up doped regions are alternately arranged along a third direction (Fig. 2B shows N+, P+, and N+ regions alternating in the X direction) and having opposite conductivity types (Shown), wherein the source contacts are connected to the source regions and the pick-up doped regions (Portion 213 of source contacts are shown connected to source regions and pick-up doped regions).
Regarding claim 9, Hsieh ‘760 discloses wherein the interlayer dielectric layer covers the source regions and the pick-up doped regions (Fig. 2B show interlayer dielectric layer 214 covering source regions and pick-up doped regions).
Allowable Subject Matter
Claim 10 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The prior art of record does not disclose The semiconductor device as claimed in claim 3, wherein the silicon carbide substrate has a third region and a fourth region, and the semiconductor device further comprises: a third electrode disposed in the epitaxial layer in the third region and extending along the first direction, wherein the third electrode is electrically connected to the source contacts; a third gate disposed in the epitaxial layer in the third region and connected to the split gate structure, wherein the third gate extends from opposite sidewalls of the third electrode to cover a third electrode top surface of the third electrode and a top surface of the epitaxial layer; a gate contact extending from above the epitaxial layer in the third region into the third gate and electrically connected to the third gate; a gate metal layer disposed on the epitaxial layer in the third region, wherein the gate metal layer covers and is electrically connected to the gate contact; and a fourth electrode disposed in the epitaxial layer in the fourth region and extending along the first direction, wherein the fourth electrode is electrically connected to the source contacts, wherein the well region is located in the epitaxial layer in the third region and the fourth region, and the interlayer dielectric layer covers the third electrode and the fourth electrode. Specifically, the prior art of record does not disclose the third electrode being electrically connected to the source contacts, a third gate connected to the split gate structure and covering a third electrode top surface of the third electrode and a top surface of the epitaxial layer, and wherein the fourth electrode is electrically connected to the source contacts.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMUEL J SMITH whose telephone number is (703)756-5706. The examiner can normally be reached M-F 8-5 EST.
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/S.J.S./Examiner, Art Unit 2817
/ALI NARAGHI/Primary Examiner, Art Unit 2817
