Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 6-10, and 15-16 are rejected under 35 U.S.C. 102(a)(1) as being unpatentable by Tsai et al. (US-20210391272-A1 referred as Tsai).
Regarding claim 1. Tsai discloses a semiconductor device, comprising:
an interposer ([0013], figure 1a, a interposer #C1 is illustrated);
a plurality of chiplets directly bonded to the interposer ([0013], figure 1a, a plurality of chiplets #110 are directly bonded to the interposer #C1);
a plurality of interposer dies directly bonded to the interposer adjacent the plurality of chiplets ([0013], figure 1a, a plurality of interposer dies #120a/120b is directly bonded to the interposer #C1 and is adjacent to the plurality of chiplets #110), the plurality of interposer dies comprising through substrate vias ([0018, 0021], figure 1a, the plurality of interposer dies #120a/120b includes substrate vias #126a/126b as described); and
a memory package over and bonded at least one of the plurality of interposer dies ([0031], figure 1c, a memory package #160 is over and bonded to atleast one of the plurality of interposer dies #120b).
Regarding claim 6. Tsai discloses a redistribution structure over the interposer, the redistribution structure including dielectric layers and metallization layers ([0029], figure 1b, a redistribution structure #140 is over the interposer #C1 and it further includes dielectric layers and metallization layers as described).
Regarding claim 7. Tsai discloses wherein the interposer further comprises an interconnect structure with multiple dielectric layers and metallization layers, the metallization layers being electrically coupled to the plurality of chiplets and the plurality of interposer dies ([0029], figure 1b, the interposer #C1 further comprises an interconnect structure #140 with multiple dielectric and metallization layers, as described, and the metallization layers are electrically coupled to the plurality of chiplets #110 and the plurality of interposer dies #120a/120b as illustrated).
Regarding claim 8. Tsai discloses wherein the memory package is bonded to the at least one of the plurality of interposer dies using a micro bump bonding structure ([0031], figure 1c, the memory package #160 is bonded to atleast one of the plurality of interposer dies #120b using a microbump bonding structure #162).
Regarding claim 9. Tsai discloses a method, comprising:
directly bonding a plurality of chiplets to an interposer ([0013], figure 1a, a plurality of chiplets #110 is directly bonded to the interposer #C1 using die attachment);
directly bonding a plurality of interposer dies to the interposer adjacent the plurality of chiplets ([0013], figure 1a, a plurality of interposer dies #120a/120b is directly bonded to the interposer #C1 using die attachment), wherein the plurality of interposer dies comprise through substrate vias ([0018, 0021], figure 1a, the plurality of interposer dies #120a/120b includes substrate vias #126a/126b as described); and
bonding a memory package over and to at least one of the plurality of interposer dies using a solder connection ([0013], figure 1a, a memory package #160 is over and bonded to atleast one of the plurality of interposer dies #120b by using a solder connection through #162 which is known in the art to couple connections).
Regarding claim 10. Tsai discloses wherein directly bonding the plurality of chiplets to the interposer comprises metal-to-metal bonding and dielectric-to-dielectric bonding ([0013], figure 1a, the plurality of chiplets #110 directly bonding to the interposer #C1 uses die attachment films which bonds the metal to metal bonding and dielectric to dielectric bonding).
Regarding claim 15. Tsai discloses forming an interconnect structure over the interposer, the interconnect structure comprising dielectric layers and metallization layers, the metallization layers of the interconnect structure being electrically coupled to the plurality of chiplets and the plurality of interposer dies ([0029], figure 1b, the interposer #C1 further comprises an interconnect structure #140 with multiple dielectric and metallization layers, as described, and the metallization layers are electrically coupled to the plurality of chiplets #110 and the plurality of interposer dies #120a/120b as illustrated).
Regarding claim 16. Tsai discloses wherein bonding the memory package to the at least one of the plurality of interposer dies includes using a micro bump bonding structure ([0031], figure 1c, the memory package #160 is bonded to atleast one of the plurality of interposer dies #120b using a microbump bonding structure #162).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Tsai et al. (US-20210391272-A1 referred as Tsai) in view of Kuo et al. (US-20220223491-A1 referred as Kuo).
Regarding claim 2, claim 4 and claim 5. Tsai lacks
[claim 2] wherein the interposer comprises a silicon material.
[claim 5] wherein the memory package comprises a dynamic random-access memory (DRAM) package.
Kuo discloses
[claim 2] wherein the interposer comprises a silicon material ([0023], figure 1, the interposer #102 comprises of silicon material as described).
[claim 5] wherein the memory package comprises a dynamic random-access memory (DRAM) package ([0044], figure 1, the memory package #126 comprises of a DRAM as described).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Tsai to include further describing the interposer including silicon material and for the memory package to comprise of DRAM as taught by Kuo in order to increase the devices efficiency, reduce the manufacturing costs of inexpensive components, and to enhance the processing power of the device.
Claims 3 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Tsai et al. (US-20210391272-A1 referred as Tsai) in view of We et al. (US-20230163112-A1 referred as We).
Regarding claim 3 and claim 11. Tsai lacks
[claim 3] wherein the plurality of chiplets includes at least one processor chiplet and at least one memory chiplet.
[claim 11] wherein directly bonding the plurality of chiplets to the interposer includes bonding at least one processor chiplet and at least one memory chiplet.
We discloses
[claim 3] wherein the plurality of chiplets includes at least one processor chiplet and at least one memory chiplet ([0027], figure 1, the plurality of chiplets #104(1)/104(2) includes one processor chiplet #104(1) and one memory chiplet #104(2) as described).
[claim 11] wherein directly bonding the plurality of chiplets to the interposer includes bonding at least one processor chiplet and at least one memory chiplet ([0027], figure 1, the bonding of plurality of chiplets #104(1)/104(2) includes one processor chiplet #104(1) and one memory chiplet #104(2) as described).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Tsai to include wherein the plurality of chiplets includes at least one processor chiplet and at least one memory chiplet as taught by We in order to have a greater memory bandwidth, lowered latency, and with an improved overall performance.
Claim 4 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Tsai et al. (US-20210391272-A1 referred as Tsai) in view of Lai et al. (US-20160322323-A1 referred as Lai).
Regarding claim 4 and claim 12. Tsai lacks
[claim 4] wherein the plurality of interposer dies includes passive components selected from the group consisting of capacitors, resistors, and inductors.
[claim 12] wherein directly bonding the plurality of interposer dies to the interposer includes integrating passive components into the plurality of interposer dies, the passive components selected from the group consisting of capacitors, resistors, and inductors.
Lai discloses
[claim 4] wherein the plurality of interposer dies includes passive components selected from the group consisting of capacitors, resistors, and inductors ([0037], figure 3, the interposer dies #3 includes passive components such as capacitors, resistor, and inductors).
[claim 12] wherein directly bonding the plurality of interposer dies to the interposer includes integrating passive components into the plurality of interposer dies, the passive components selected from the group consisting of capacitors, resistors, and inductors ([0037], figure 3, the interposer dies #3 includes passive components within the interposer such as capacitors, resistor, and inductors).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Tsai to include wherein the interposer dies includes passive components selected from the group consisting of capacitors, resistors, and inductors as taught by Lai in order to have an improved power integrity, reduce the device size, and to enhance the clarity of the signal within the circuit.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Tsai et al. (US-20210391272-A1 referred as Tsai) in view of Semmelmeyer et al. (US-20130187292-A1 referred as Semmelmeyer).
Regarding claim 13. Tsai lacks wherein the plurality of interposer dies may include transistors.
Semmelmeyer discloses wherein the plurality of interposer dies may include transistors ([0028], figure 1, the interposer dies #18 include transistors within as described).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Tsai to include wherein the interposer dies may include transistors as taught by Semmelmeyer in order to have an improved active signal processing, enhanced integration support, and to have a lower latency.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Tsai et al. (US-20210391272-A1 referred as Tsai) in view of Wu et al. (US-20210366805-A1 referred as Wu).
Regarding claim 14. Tsai lacks attaching a support substrate over the plurality of chiplets with a thermal interface material, the memory package being adjacent the support substrate.
Wu discloses attaching a support substrate over the plurality of chiplets with a thermal interface material, the memory package being adjacent the support substrate ([0024, 0030], figure 1, attaching a support substrate #400 with thermal interface material, as described, over the plurality of chiplets #100/200. The memory package #120 (contains memory as described in [0024]) is seen adjacent in some parts to the support substrate #400).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Tsai to include attaching a support substrate over the plurality of chiplets with a thermal interface material as taught by Wu in order to have an improved thermal management, improved device integrity, and with an extended device lifetime.
Claims 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Tsai et al. (US-20210391272-A1 referred as Tsai) in view of Kuo et al. (US-20220223491-A1 referred as Kuo).
Regarding claim 17. Tsai discloses a method, comprising:
bonding with a direct bonding process a plurality of integrated circuit dies to an interposer ([0013], figure 1a, a plurality of integrated circuit dies #120a/120b is directly bonded to the interposer #C1), the interconnect structure comprising dielectric layers and metallization layers ([0029], figure 1c, the interconnect structure #140 comprises of dielectric layers and metallization layers as described);
bonding a memory package over the plurality of integrated circuit dies ([0031], figure 1c, bonding a memory package #160 over the plurality of integrated circuit dies #120b through the interconnect structure #140).
Tsai lacks the interposer comprising through substrate vias and an interconnect structure over the through substrate vias; and forming an electrical connection between the interconnect structure of the interposer and the memory package, the electrical connection being adjacent the plurality of integrated circuit dies.
Kuo discloses the interposer comprising through substrate vias and an interconnect structure over the through substrate vias ([0038], figure 1, the interposer #102 comprises through substrate vias within (as illustrated) and an interconnect structure #114/116/120 over the through substrate vias); and forming an electrical connection between the interconnect structure of the interposer and the memory package ([0038], figure 1, forming an electrical connection between the interconnect structure #114/116/120/122 of the interposer #102 and the memory package #124/126 (described as memory in [0044]). Please note to clarify, the electrical connection in between the interposer #102 and the memory package #124/126 goes through the conductive path of #102/114/116/120/122), the electrical connection being adjacent the plurality of integrated circuit dies ([0023], figure 1a, the electrical connection of #102/114/116/120/122 is adjacent to the plurality of integrated circuit dies #108/112).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Tsai to include forming an electrical connection between the interconnect structure of the interposer and the memory package as taught by Kuo in order to have an have an improved device versatility, create a more compact frame, and to provide a consistent electrical connection within the device.
Regarding claim 18. Tsai as modified discloses bonding a plurality of interposer dies with a direct bonding process to the interposer ([0013], figure 1a, bonding a plurality of interposer dies #110 to the interposer #C1), the electrical connection between the interconnect structure of the interposer and the memory package comprising through substrate vias in the plurality of interposer dies ([0013], figure 1a, the electrical connection between the interconnect structure #140 of the interposer #C1 and the memory package #160 comprising through substrate vias #126b in the plurality of interposer dies #110).
Regarding claim 19. Tsai as modified discloses encapsulating the plurality of integrated circuit dies with an encapsulant ([0032], figure 1d, encapsulating the plurality of integrated circuit dies #110 with an encapsulant #170/130); and forming through dielectric vias through the encapsulant, the electrical connection between the interconnect structure of the interposer and the memory package comprising the through dielectric vias ([0032], figure 1d, forming through dielectric vias #162 through the encapsulant #170/130 and making an electrical connection between the interconnect structure #140 of the interposer #C1 through the dielectric vias #162).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Tsai et al. (US-20210391272-A1 referred as Tsai) and Kuo et al. (US-20220223491-A1 referred as Kuo) in further view of Wu et al. (US-20210366805-A1 referred as Wu).
Regarding claim 20. Tsai as modified lacks attaching a support substrate over the plurality of integrated circuit dies with a thermal interface material, the memory package being adjacent to the support substrate.
Wu discloses attaching a support substrate over the plurality of integrated circuit dies with a thermal interface material, the memory package being adjacent to the support substrate ([0024, 0030], figure 1, attaching a support substrate #400 with thermal interface material, as described, over the plurality of chiplets #100/200. The memory package #120 (contains memory as described in [0024]) is seen adjacent in some regions to the support substrate #400).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Tsai to include attaching a support substrate over the plurality of integrated circuit dies with a thermal interface material as taught by Wu in order to have an improved thermal management, improved device integrity, and with a extended device lifetime.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure includes Chen et al. (US-20230326819-A1) and Hu et al. (US-20230260896-A1) for teaching the memory dies, interconnection structures, and substrate vias.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB R MARIN whose telephone number is (571)272-5887. The examiner can normally be reached Monday to Friday from 8:30am - 5:00pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff Natalini can be reached at (571) 272 - 2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JACOB RAUL MARIN/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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