DETAILED ACTION
This Notice is responsive to communication filed on 5/31/2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/13/2024 and 2/20/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant's election with traverse of Group I invention, reading on claims 1-11 in the reply filed on 7/27/2026 is acknowledged. The traversal is on the ground(s) that it should be no undue burden on the Examiner to consider all claims in the single application. This is not found persuasive because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement.
The requirement is still deemed proper and is therefore made FINAL.
Claims 12-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 7/27/2026.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the claim limitation "further comprising: an interlayer dielectric layer disposed in the epitaxial layer in the second region and the third region, wherein the top portion of the first electrode, the source regions, the pick-up doped regions and a top surface of the third gate electrode are exposed from the interlayer dielectric layer" must be shown or the feature(s) canceled from the claim(s). As it currently shows in Fig. 1, the interlayer dielectric layer is disposed in the second and third region, and only the third gate electrode is defined as being disposed in the second region or third region. The top portion of the first electrode, the source regions, and the pick-up doped regions are all shown to be in the first region. Therefore, the claim that the top portion of the first electrode, the source regions, and the pick-up doped regions are exposed from the interlayer dielectric layer is not shown in the drawings.
No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 11, the claim limitation recites “an interlayer dielectric layer disposed in the epitaxial layer in the second region and the third region, wherein the top portion of the first electrode, the source regions, the pick-up doped regions and a top surface of the third gate electrode are exposed from the interlayer dielectric layer. Per this claim, the interlayer dielectric layer is disposed in the second and third region, and only the third gate electrode is defined as being disposed in the second region or third region. Therefore, the claim that the top portion of the first electrode, the source regions, and the pick-up doped regions are exposed from the interlayer dielectric layer is indefinite.
A claim, although clear on its face, may also be indefinite when a conflict or inconsistency between the claimed subject matter and the specification disclosure renders the scope of the claim uncertain as inconsistency with the specification disclosure or prior art teachings may make an otherwise definite claim take on an unreasonable degree of uncertainty. In re Moore, 439 F.2d 1232, 1235-36, 169 USPQ 236, 239 (CCPA 1971).
For the purpose of this examination, claim 11 will be interpreted as the top portion of the first electrode, the source regions, and the pick-up doped regions are exposed from the gate dielectric layer, and a top surface of the third gate electrode is exposed from the interlayer dielectric layer.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4 and 6-9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yedinak et al. (US 20090008709).
Regarding claim 1, Yedinak discloses a semiconductor device, comprising:
a silicon carbide substrate Fig. 33A: n++,
wherein the silicon carbide substrate Fig. 33A: n++ has a first region, a second region and a third region (annotated below), and has a first conductivity type (i.e. n-type);
an epitaxial layer Fig. 33A: 3306 disposed on a top surface of the silicon carbide substrate Fig. 33A: n++ (para. 0162 teaches silicon carbide material),
wherein the epitaxial layer Fig. 33A: 3306 has the first conductivity type (i.e. n-type);
a first electrode Fig. 33A: 3311 disposed in the epitaxial layer Fig. 33A: 3306 in the first region and extending in a first direction (para. 0161, extends vertically);
a split gate structure (para. 0161 teaches split gate structure) disposed in the epitaxial layer Fig. 33A: 3306 in the first region,
wherein the split gate structure comprises:
a first gate electrode Fig. 33A: 3310 and a second gate electrode Fig. 33A: 3310 separated from each other and located on opposite sidewalls of the first electrode Fig. 33A: 3311,
wherein a top portion of the first electrode Fig. 33A: 3311 is exposed from the split gate structure (shown in Fig. 33A); and
a source contact Fig. 33A: S disposed on the epitaxial layer Fig. 33A: 3306 in the first region,
wherein the source contact Fig. 33A: S covers and is electrically connected to the top portion of the first electrode Fig. 33A: 3311 (shown in Fig. 33A; abstract teaches electrical contact to the shield electrode 3311 made in the active region; para. 0160 teaches contact between source region and electrodes).
PNG
media_image1.png
475
714
media_image1.png
Greyscale
PNG
media_image2.png
542
674
media_image2.png
Greyscale
Regarding claim 2, Yedinak discloses the semiconductor device as claimed in claim 1, wherein the split gate structure further comprises: a gate dielectric layer Fig. 33M: 3308 disposed in the epitaxial layer Fig. 33A: 3306 in the first region and surrounding the first gate electrode Fig. 33A: 3310 and the second gate electrode Fig. 33A: 3310, wherein the top portion of the first electrode Fig. 33A: 3311 protrudes from a top surface of the gate dielectric layer Fig. 33M: 3308.
Regarding claim 3, Yedinak discloses the semiconductor device as claimed in claim 2, wherein the gate dielectric layer Fig. 33M: 3308 has: a first portion located between the first gate electrode Fig. 33A: 3310 and the first electrode Fig. 33A: 3311; and a second portion located between a first gate top surface of the first gate electrode Fig. 33A: 3310 and the top surface of the gate dielectric layer Fig. 33M: 3308, wherein the first portion has a first thickness in a second direction, the second portion has a second thickness in the first direction, and a ratio of the second thickness to the first thickness is between 2 and 3 (annotated Fig. 33A below; para. 0192 teaches a thickness of the IPD layer, the inter poly dielectric layer, that has a ratio in the range between 2 and 5, which includes the range taught in claim 3).
PNG
media_image3.png
530
480
media_image3.png
Greyscale
Regarding claim 4, Yedinak discloses the semiconductor device as claimed in claim 2, further comprising: a well region (annotated Fig. 33A) located in the epitaxial layer Fig. 33A: 3306, wherein the well region has a second conductivity type(i.e. p-type); and source regions and pick-up doped regions (annotated Fig. 33A) located on the well region in the first region and close to a top surface of the epitaxial layer Fig. 33A: 3306, wherein the source regions and the pick-up doped regions are alternately arranged along a third direction and have opposite conductivity types, and wherein the source contact covers and is electrically connected to the source regions and the pick-up doped regions (see annotated Fig. 1 above, Sample First Region).
Regarding claim 6, Yedinak discloses the semiconductor device as claimed in claim 4, wherein the source contact Fig. 33A: S has a first lower surface, a second lower surface and a third lower surface, and wherein the first lower surface is connected to the top portion of the first electrode Fig. 33A: 3311, the second lower surface is connected to the gate dielectric layer Fig. 33M: 3308, and the third lower surface is connected to the source regions and the pick-up doped regions (annotated below).
PNG
media_image4.png
356
659
media_image4.png
Greyscale
Regarding claim 7, Yedinak discloses the semiconductor device as claimed in claim 6, wherein the first lower surface and the second lower surface are not coplanar with each other (shown in annotated Fig. 33A above).
Regarding claim 8, Yedinak discloses the semiconductor device as claimed in claim 6, wherein the first lower surface and the third lower surface of the source contact Fig. 33A: S are formed of a first metal silicide (para. 0225 teaches silicide contacts formed after the deposition of the gate polys (gate electrodes), the shield electrode (first electrode), and dielectric layers).
Regarding claim 9, Yedinak discloses the semiconductor device as claimed in claim 1, wherein the first electrode Fig. 33A: 3311 extends from below the first gate electrode Fig. 33A: 3310 and the second gate electrode Fig. 33A: 3310 to above the first gate electrode Fig. 33A: 3310 and the second gate electrode Fig. 33A: 3310 along the first direction and is inserted between the first gate electrode Fig. 33A: 3310 and the second gate electrode Fig. 33A: 3310 along a second direction (shown in Fig. 33A).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference(s).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Yedinak et al. (US 20090008709) as applied to claim 1 above, and further in view of Hsieh (US 20130168760).
Regarding claim 5, Hsieh discloses the following claim limitations not explicitly disclosed by Yedinak:
the semiconductor device as claimed in claim 4, wherein
the source contact Fig. 2B: 215 has a first sidewall and a second sidewall opposite to each other (annotated below),
the first sidewall is adjacent to the first electrode Fig. 2B: 207, and
the second sidewall is adjacent to the source regions Fig. 2B: n+ (see Fig. 2A: 211) and the pick-up doped regions Fig. 2B: p+ (see Fig. 2A: 216).
PNG
media_image5.png
414
561
media_image5.png
Greyscale
It would be obvious to one of ordinary skill in the act before the effective filing date of the invention, to modify Yedinak with Hsieh in order to connect the source electrode (first electrode) to a source metal and further reduce the contact resistance between the contact metal plug (source contact) and the p body region (well region) (para. 0027).
Claims 10 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Yedinak et al. (US 20090008709) as applied to claim 1 above, and further in view of Kraft et al. (US 20090057754).
Regarding claim 10, Yedinak teaches the following claim limitations:
the semiconductor device as claimed in claim 4, further comprising,
a second electrode (annotated Fig. 33M below) disposed in the epitaxial layer in the second region and extending in the first direction,
wherein the second electrode is electrically connected to the source contact (shown in Fig. 33M);
a third gate electrode (annotated below) disposed in the epitaxial layer in the second region and connected to the split gate structure,
wherein the third gate electrode extends from the opposite sidewall of the second electrode to cover a second electrode top surface of the second electrode and the top surface of the epitaxial layer;
a gate contact disposed on the epitaxial layer in the second region,
wherein the gate contact covers and is electrically connected to the third gate electrode; and
a third electrode (annotated below) disposed in the epitaxial layer in the third region and extending in the first direction,
wherein the third electrode is electrically connected to the source contact (shown in Fig. 33A; abstract teaches electrical contact to the shield electrode 3311 made in the active region; para. 0160 teaches contact between source region and electrodes).
PNG
media_image6.png
503
789
media_image6.png
Greyscale
Kraft discloses the following claim limitations not disclosed by Yedinak:
wherein the third gate electrode Fig. 2H: 222 extends from the opposite sidewall of the second electrode Fig. 2H: 214 to cover a second electrode top surface of the second electrode Fig. 2H: 214 and the top surface of the epitaxial layer (shown in Fig. 22H);
a gate contact Fig. 2H: 226B disposed on the epitaxial layer in the second region (para. 0024),
wherein the gate contact Fig. 2H: 226B covers and is electrically connected to the third gate electrode Fig. 2H: 222 (para. 0024-25).
It would be obvious to one of ordinary skill in the art before the effective filing date of the invention, to modify Yedinak with Kraft for the purpose of connecting and biasing the shield electrode (second electrode) to the same potential as the gate electrode, obtaining a low on-resistance for the same breakdown voltage, and eliminating the need for a high-quality IED (para. 0025).
Regarding claim 11, as aforementioned, the claim rejected as being indefinite will be rejected as interpreted above.
NOTE: Modified portions will be bolded below.
Yedinak discloses the semiconductor device as claimed in claim 10, further comprising:
an interlayer dielectric layer disposed in the epitaxial layer in the second region and the third region (annotated below),
wherein the top portion of the first electrode, the source regions, the pick-up doped regions are exposed from the gate dielectric layer in the first region (see Fig. 33A for detailed view), and
a top surface of the third gate electrode is exposed from the interlayer dielectric layer.
Kraft discloses the following claim limitations not disclosed by Yedinak:
a top surface of the third gate electrode Fig. 22H: 222 is exposed from the interlayer dielectric layer Fig. 22H: 216 (i.e. gate dielectric layer shown in Fig. 22H).
It would be obvious to one of ordinary skill in the art before the effective filing date of the invention, to modify Yedinak with Kraft having a process that forms a gate dielectric layer that further effectively eliminates additional steps and simplify the process of forming a high-quality IED (para. 0029).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NKECHINYERE ESIABA whose telephone number is (571)272-0720. The examiner can normally be reached Monday - Friday 10am-5pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Nkechinyere Esiaba/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
Prosecution Insights