Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Currently, claims 1-20 are pending and examined below.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: DISPLAY DEVICE HAVING CIRCUIT BOARDS CONNECTED TO DISPLAY PANEL
Information Disclosure Statement (IDS)
The information disclosure statement submitted on 05/31/2024 ("05-31-24 IDS") is in compliance with the provisions of 37 CFR 1.97. Accordingly, the 05-31-24 IDS is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 17-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Independent claim 17 is indefinite because it is unclear what “the display pane” is referring to. For the purpose of advancing the examination of the instant application, “the display pane” has been interpreted as “the display panel” as “a display panel” has been recited in line 2 of the claim 17.
Claims 18-20 are indefinite, because they depend from the indefinite claim 17.
Claim Rejections - 35 USC § 1021
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-7, 13-16, 17 and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pub. No. US 2021/0247820 A1 to Oh et al. ("Oh").
Fig. 2A and Fig. 4B of Oh have been annotated and Fig. 3B has been provided to support the rejection below:
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Regarding independent claim 1, Oh teaches a display device (see Fig. 1; see also Figs. 2A, 3A, 4A and 4B for example) comprising:
a first circuit board FPCB1 (para [0044] - “Referring to FIGS. 1 to 2, a display apparatus DD may include a display panel DP, a flexible circuit board FPCB, and a main circuit board MPCB”);
a second circuit board FPCB2; and
a display panel DP electrically connected to the first circuit board FPCB1 and the second circuit board FPCB2, defining a display area DA and a non-display area NDA; and comprising:
a base layer 100 (para [0047] - “[0047] The display panel DP may include a first display substrate 100 and a second display substrate 200.”; see Fig. 3A and Fig. 4B) comprising:
a first sub-base layer 10 overlapping the display area DA and the non-display area NDA (see Fig. 3A);
a second sub-base layer 30 (see Fig. 3A and Fig. 4B) above the first sub-base layer 10;
a connection electrode GE, DE2 or SE2 (para [0083] - “FIG. 3B exemplarily illustrates an arrangement relationship between a first semiconductor pattern OSP1, a second semiconductor pattern OSP2, a first control electrode GE1, a second control electrode GE2, a first input electrode DE1, a first output electrode SE1, a second input electrode DE2, and a second output electrode SE2, which constitute the switching transistor T1 and the driving transistor T2. First to fourth through-holes CH1, CH2, CH3, and CH4 are also exemplarily illustrated.”) between the first sub-base layer 10 and the second sub-base layer 30, and electrically connected to a signal line PL-D (see Fig. 2A; Referring to FIG. 4B, according to an embodiment of the inventive concept, display pads PD1-P and PD2-P may be connected to different auxiliary signal lines PL-D through contact holes CH-1 and CH-2 passing through the first to fourth insulation layers 10 to 40.”); and
pad electrodes PL1-P of FPCB1, PL1-P of FPCB2 exposed through an opening defined in the first sub-base layer 10 (Fig. 2A showing five PDA areas each of which is represented by Fig. 4B.), electrically connected to the connection electrode GE2, DE2 or SE2 (via PL-D at CH), and comprising:
first pad electrodes PL1-P of FPCB1 electrically connected to the first circuit board FPCB1, and extending in a first direction DR1; and
second pad electrodes PL1-P of FPCB2 electrically connected to the second circuit board FPCB2, spaced apart from the first pad electrodes PL1-P of FPCB1 in the first direction DR1, and extending in an opposite direction DR2 to the first direction DR1; and
a circuit layer DC (para [0055] - “[0055] The flexible circuit board FPCB may include a driving chip DC. The flexible circuit board FPCB may transmit a signal from the main circuit board MPCB to the driving chip DC and a signal from the driving chip DC to the display panel DP.” When the FPCB is flattened, the driving chip DC would above the base layer 100.) above the base layer 100, and comprising a transistor (a driving chip DC more likely than not includes a transistor.), and at least one signal line DL1 or GL1 connected to the transistor.
Or,
Oh teaches a display device (see Fig. 1; see also Figs. 2A, 3A, 4A and 4B for example) comprising:
a first circuit board FPCB1 (para [0044] - “Referring to FIGS. 1 to 2, a display apparatus DD may include a display panel DP, a flexible circuit board FPCB, and a main circuit board MPCB”);
a second circuit board FPCB2; and
a display panel DP electrically connected to the first circuit board FPCB1 and the second circuit board FPCB2, defining a display area DA and a non-display area NDA; and comprising:
a base layer 100 (para [0047] - “[0047] The display panel DP may include a first display substrate 100 and a second display substrate 200.”; see Fig. 3A and Fig. 4B) comprising:
a first sub-base layer 10 overlapping the display area DA and the non-display area NDA (see Fig. 3A);
a second sub-base layer 30 (see Fig. 3A and Fig. 4B) above the first sub-base layer 10;
a connection electrode GE2, DE2 or SE2 (para [0083] - “FIG. 3B exemplarily illustrates an arrangement relationship between a first semiconductor pattern OSP1, a second semiconductor pattern OSP2, a first control electrode GE1, a second control electrode GE2, a first input electrode DE1, a first output electrode SE1, a second input electrode DE2, and a second output electrode SE2, which constitute the switching transistor T1 and the driving transistor T2. First to fourth through-holes CH1, CH2, CH3, and CH4 are also exemplarily illustrated.”) between the first sub-base layer 10 and the second sub-base layer 30, and electrically connected to a signal line PL-D (see Fig. 2A; Referring to FIG. 4B, according to an embodiment of the inventive concept, display pads PD1-P and PD2-P may be connected to different auxiliary signal lines PL-D through contact holes CH-1 and CH-2 passing through the first to fourth insulation layers 10 to 40.”); and
pad electrodes PL1-P of FPCB1, PL1-P of FPCB2 exposed through an opening defined in the first sub-base layer 10 (Fig. 2A showing five PDA areas each of which is represented by Fig. 4B.), electrically connected to the connection electrode GE2, DE2 or SE2 (via PL-D at CH), and comprising:
first pad electrodes PL1-P of FPCB1 electrically connected to the first circuit board FPCB1, and extending in a first direction; and
second pad electrodes PL1-P of FPCB2 electrically connected to the second circuit board FPCB2, spaced apart from the first pad electrodes PL1-P of FPCB1 in the first direction DR1, and extending in an opposite direction DR2 to the first direction DR1; and
a circuit layer PE (see Fig. 3A) above the base layer 100, and comprising a transistor TR, and at least one signal line DL1 or GL1 connected to the transistor TR (see Fig. 2A).
Regarding claim 2, Oh teaches the first circuit board FPCB1 that comprises a first base film IL or SR (para [0096] - “The flexible circuit board FPCB may include an insulation layer IL, a substrate signal line SL, a solder resist layer SR, and substrate pads F-PD1 and F-PD2.”), and a first bump electrode F-PD1 above the first base film IL or SR, and
wherein the second circuit board FPCB2 comprises a second base film IL or SR, and a second bump electrode F-PD1 above the second base film IL or SR.
Regarding claim 3, Oh teaches the first circuit board FPCB1 that comprises a first base film IL or SR (para [0096] - “The flexible circuit board FPCB may include an insulation layer IL, a substrate signal line SL, a solder resist layer SR, and substrate pads F-PD1 and F-PD2.”), and a first bump electrode F-PD1 above the first base film IL or SR, and
wherein the second circuit board FPCB2 comprises a second base film IL or SR, and a second bump electrode F-PD1 above the second base film IL or SR an facing the first bump electrodes F-PD1 (of FPCB1) in the first direction DR1.
Regarding claim 4, Oh teaches the first pad electrodes PL1-P of FPCB1 respectively contact the first bump electrodes F-PD1 of FPCB1, and
wherein the second pad electrodes PL1-P of FPCB1 respectively contact the second bump electrodes F-PD1 of FPCB2.
Regarding claim 5, Oh teaches the first bump electrode F-PD1 of FPCB1 that comprises a first contact part extending beyond an edge of the first base film SR, and
wherein the second bump electrode F-PD1 of FPCB2 comprises a second contact part extending beyond an edge of the second base film SR.
Regarding claim 6, Oh teaches a first metal pattern ACF or SL electrically connecting the first bump electrode F-PD1 of FPCB1 and the first pad electrodes PL1-P of FPCB1; and
a second metal pattern ACF or SL electrically connecting the second bump electrode F-PD1 of FPCB2 and the second pad electrodes PL1-P of FPCB2;
wherein the first metal pattern ACF or SL (para [0096] - “a substrate signal line SL”; para [0097] - “anisotropic conductive film ACF”) electrically contacts the first pad electrodes PL1-P of FPCB1 and the first contact part, and
wherein the second metal pattern ACF or SL contacts the second pad electrodes PL1-P of FPCB2 and the second contact part.
Regarding claim 7, Oh teaches a first adhesive layer ACF between the first bump electrode F-PD1 of FPCB1 and the first pad electrodes PL1-P of FPCB1;
a second adhesive layer ACF between the second bump electrode F-PD1 of FPCB2 and the second pad electrodes PL1-P of FPCB2.
Regarding claim 13, Oh teaches the first circuit board FPCB1 that comprises a bending part bent towards a lower side of the display panel DP (see Fig. 2B), and
wherein a portion of the first circuit board FPCB1 overlaps the second circuit board FPCB2 on a plane (that encompasses direction DR2 and having a normal vector in the DR1 direction) (see Fig. 1).
Regarding claim 14, Oh teaches the first pad electrodes PL1-P of FPCB1 and the second pad electrodes PL1-P of FPCB2 that overlap the non-display area NDA.
Regarding claim 15, Oh teaches an insulating layer 20 between the pad electrodes PL1-P of FPCB1, PL1-P of FPCB2 and the connection electrode DE2 or SE2, the pad electrodes PL1-P of FPCB1, PL1-P of FPCB2 and the connection electrode DE2 or SE2being electrically connected through a contact hole defined by the insulating layer 20.
Regarding independent claim 17, Oh teaches a display device (see Fig. 1; see also Figs. 2A, 3A, 4A and 4B for example) comprising:
a display panel DP defining a display area DA and a non-display area NDA; and
a first circuit board FPCB1 (para [0044] - “Referring to FIGS. 1 to 2, a display apparatus DD may include a display panel DP, a flexible circuit board FPCB, and a main circuit board MPCB”) electrically connected to the display panel DP, and a second circuit board FPCB2 electrically connected to the display pane DP and spaced apart from the first circuit board FPCB1 in a first direction DR1;
wherein the display panel DP comprises:
a base layer 100 (para [0047] - “[0047] The display panel DP may include a first display substrate 100 and a second display substrate 200.”; see Fig. 3A and Fig. 4B) comprising:
a first sub-base layer 10 overlapping the display area DA and the non-display area NDA (see Fig. 3A);
a second sub-base layer 30 (see Fig. 3A and Fig. 4B) above the first sub-base layer 10;
a connection electrode GE, DE2 or SE2 (para [0083] - “FIG. 3B exemplarily illustrates an arrangement relationship between a first semiconductor pattern OSP1, a second semiconductor pattern OSP2, a first control electrode GE1, a second control electrode GE2, a first input electrode DE1, a first output electrode SE1, a second input electrode DE2, and a second output electrode SE2, which constitute the switching transistor T1 and the driving transistor T2. First to fourth through-holes CH1, CH2, CH3, and CH4 are also exemplarily illustrated.”) between the first sub-base layer 10 and the second sub-base layer 30, and electrically connected to a signal line PL-D (see Fig. 2A; Referring to FIG. 4B, according to an embodiment of the inventive concept, display pads PD1-P and PD2-P may be connected to different auxiliary signal lines PL-D through contact holes CH-1 and CH-2 passing through the first to fourth insulation layers 10 to 40.”); and
pad electrodes PL1-P of FPCB1, PL1-P of FPCB2 exposed through an opening defined in the first sub-base layer 10 (Fig. 2A showing five PDA areas each of which is represented by Fig. 4B.), electrically connected to the connection electrode GE2, DE2 or SE2 (via PL-D at CH), and comprising:
first pad electrodes PL1-P of FPCB1 overlapping the first circuit board FPCB1 and not overlapping the second circuit board FPCB1; and
second pad electrodes PL1-P of FPCB2 overlapping the second circuit board FPCB2 and not overlapping the second circuit board FPCB2, at least one of the second pad electrodes PL1-P of FPCB2 facing at least one of the first pad electrodes PL1-P of FPCB1 in a second direction DR2 that is substantially perpendicular to the first direction DR1; and
a circuit layer DC (para [0055] - “[0055] The flexible circuit board FPCB may include a driving chip DC. The flexible circuit board FPCB may transmit a signal from the main circuit board MPCB to the driving chip DC and a signal from the driving chip DC to the display panel DP.” When the FPCB is flattened, the driving chip DC would above the base layer 100.) above the base layer 100, and comprising a transistor (a driving chip DC more likely than not includes a transistor.), and at least one signal line DL1 or GL1 connected to the transistor.
Or,
Oh teaches a display device (see Fig. 1; see also Figs. 2A, 3A, 4A and 4B for example) comprising:
a display panel DP defining a display area DA and a non-display area NDA; and
a first circuit board FPCB1 (para [0044] - “Referring to FIGS. 1 to 2, a display apparatus DD may include a display panel DP, a flexible circuit board FPCB, and a main circuit board MPCB”) electrically connected to the display panel DP, and a second circuit board FPCB2 electrically connected to the display pane DP and spaced apart from the first circuit board FPCB1 in a first direction DR1;
wherein the display panel DP comprises:
a base layer 100 (para [0047] - “[0047] The display panel DP may include a first display substrate 100 and a second display substrate 200.”; see Fig. 3A and Fig. 4B) comprising:
a first sub-base layer 10 overlapping the display area DA and the non-display area NDA (see Fig. 3A);
a second sub-base layer 30 (see Fig. 3A and Fig. 4B) above the first sub-base layer 10;
a connection electrode GE, DE2 or SE2 (para [0083] - “FIG. 3B exemplarily illustrates an arrangement relationship between a first semiconductor pattern OSP1, a second semiconductor pattern OSP2, a first control electrode GE1, a second control electrode GE2, a first input electrode DE1, a first output electrode SE1, a second input electrode DE2, and a second output electrode SE2, which constitute the switching transistor T1 and the driving transistor T2. First to fourth through-holes CH1, CH2, CH3, and CH4 are also exemplarily illustrated.”) between the first sub-base layer 10 and the second sub-base layer 30, and electrically connected to a signal line PL-D (see Fig. 2A; Referring to FIG. 4B, according to an embodiment of the inventive concept, display pads PD1-P and PD2-P may be connected to different auxiliary signal lines PL-D through contact holes CH-1 and CH-2 passing through the first to fourth insulation layers 10 to 40.”); and
pad electrodes PL1-P of FPCB1, PL1-P of FPCB2 exposed through an opening defined in the first sub-base layer 10 (Fig. 2A showing five PDA areas each of which is represented by Fig. 4B.), electrically connected to the connection electrode GE2, DE2 or SE2 (via PL-D at CH), and comprising:
first pad electrodes PL1-P of FPCB1 overlapping the first circuit board FPCB1 and not overlapping the second circuit board FPCB1; and
second pad electrodes PL1-P of FPCB2 overlapping the second circuit board FPCB2 and not overlapping the second circuit board FPCB2, at least one of the second pad electrodes PL1-P of FPCB2 facing at least one of the first pad electrodes PL1-P of FPCB1 in a second direction DR2 that is substantially perpendicular to the first direction DR1; and
a circuit layer PE (see Fig. 3A) above the base layer 100, and comprising a transistor TR, and at least one signal line DL1 or GL1 connected to the transistor TR (see Fig. 2A).
Regarding claim 18, Oh teaches the first pad electrodes PL1-P of FPCB1 and the second pad electrodes PL1-P of FPCB2 that are spaced apart from each other in the first direction DR1.
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter:
Claim 8 is objected to for depending on a rejected base claim 1, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 1 or the base claim 1 is amended to include all of the limitations of claim 8.
Claims 9-12 are allowable for depending from the allowable claim 8.
Claim 16 is objected to for depending on a rejected base claim 1, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 1 or the base claim 1 is amended to include all of the limitations of claim 16.
Claim 19 is rejected to for depending on a rejected base claim 1 and the intervening claim 18, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 17 and the intervening claim 18 or the base claim 17 is amended to include all of the limitations of claim 19 and the intervening claim 18; and the pending 35 U.S.C. 112(b) rejection of the base claim 17 is successfully traversed.
Claim 20 is allowable for depending from the allowable claim 19.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Pub. No. US 2026/0197936 A1 to Lin et al.
Pub. No. US 2021/0219432 A1 to Kim
Pub. No. US 2019/0369447 A1 to Chuang
Pub. No. US 2013/0342779 A1 to Jung et al.
Pub. No. US 2012/0299888 A1 to Kim et al.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL JUNG whose telephone number is (408) 918-7554. The examiner can normally be reached on 8:30 A.M. to 7 P.M.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached on (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MICHAEL JUNG/Primary Examiner, Art Unit 2817 09 September 2026
1 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status
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