CTNF 18/680,621 CTNF 87259 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15-aia AIA Claim(s) 1 is/are rejected under 35 U.S.C. 102 (a)(1)/(a)(2) as being anticipated by Su et al. (hereinafter Su, US 2024/0113159) . In regards to independent claim 1, Su teaches a semiconductor structure, comprising: a first die (202) that includes a first semiconductor substrate (214), a first integrated circuit ([0038]) disposed on the first semiconductor substrate (214), and a first metal seal ring structure disposed on the first semiconductor substrate and surrounding the first integrated circuit (302b); and a second die (206) that includes a second semiconductor substrate (210), a second integrated circuit(218) disposed on the second semiconductor substrate(210), and a second metal seal ring structure disposed on the second semiconductor substrate and surrounding the second integrated circuit (302a); wherein the second die is disposed over the first die, the second integrated circuit is electrically connected and bonded to the first integrated circuit, and the second metal seal ring structure is bonded to the first metal seal ring structure ([0134]) (Su, Fig. 9A, {0134}) . Allowable Subject Matter 12-151-07 AIA 07-97 12-51-07 Claim s 12-20 are allowed. 12-151-08 AIA 07-43 12-51-08 Claim s 2-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. 13-03 AIA The following is an examiner’s statement of reasons for allowance: . The prior art fails to disclose or teach an obvious combination of the following limitations when taken with the claim as a whole: Claim 2: wherein the second integrated circuit has a second interconnection structure disposed in the second interconnection layers, and a second redistribution structure disposed in the second redistribution layer and electrically connected to the second interconnection structure; wherein the second metal seal ring structure has a second RDL seal ring disposed in the second redistribution layer and surrounding the second redistribution structure; and wherein the second redistribution structure is bonded to the first redistribution structure, and the second RDL seal ring is bonded to the first RDL seal ring. Claim 3-10 depend upon claim 2; therefore are allowable. Claim 11:wherein the first die includes a stress guiding metal wall disposed on the first semiconductor substrate and adjacent to an edge of the first die, and extending linearly along the edge of the first die; wherein the second die includes a metal feature aligned with and bonded to the stress guiding metal wall.Claim 12: wherein the seal ring region of the first wafer includes a first seal ring group that has a first RDL seal ring in the first redistribution layer and a plurality of first interconnection-layer seal rings in the first interconnection layers, and the first RDL seal ring is connected to one of the first interconnection-layer seal rings; wherein the seal ring region of the second wafer has a second RDL seal ring in the second redistribution layer, and the second RLD seal ring is bonded to the first RDL seal ring; and wherein one of the first wafer and the second wafer has a pattern of dicing channels surrounding the seal ring region of said one of the first wafer and the second wafer. Claim 13-17 depend upon claim 2; therefore are allowable. Claim 18: wherein the seal ring region of the first wafer includes a first seal ring group that has a first RDL seal ring in the first redistribution layer and a plurality of first interconnection-layer seal rings in the first interconnection layers, and the first RDL seal ring is connected to one of the first interconnection-layer seal rings; wherein the seal ring region of the second wafer has a second RDL seal ring in the second redistribution layer, and the second RLD seal ring is bonded to the first RDL seal ring; wherein one of the first wafer and the second wafer has a pattern of dicing channels surrounding the seal ring region of said one of the first wafer and the second wafer; and wherein the dicing of the wafer stack is performed on the pattern of the dicing channels. Claim 19-20 depend upon claim 2; therefore are allowable . Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” The prior art fails to disclose or teach an obvious combination of the following limitations when taken with the claim as a whole: Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM C TRAPANESE whose telephone number is (571)270-3304. The examiner can normally be reached Monday - Friday 7am-12pm & 8pm-10pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at (571)272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /WILLIAM C TRAPANESE/Primary Examiner, Art Unit 2812 Application/Control Number: 18/680,621 Page 2 Art Unit: 2812 Application/Control Number: 18/680,621 Page 3 Art Unit: 2812
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