Prosecution Insights
Last updated: October 02, 2026
Application No. 18/684,591

IN-SITU CORE PROTECTION IN MULTI-PATTERNING

Non-Final OA §103
Filed
Feb 16, 2024
Priority
Aug 24, 2021 — provisional 63/260,536 +1 more
Examiner
NGUYEN, THANH T
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Lam Research Corporation
OA Round
1 (Non-Final)
83%
Grant Probability
Favorable
1-2
OA Rounds
2m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allowance Rate
1186 granted / 1423 resolved
+15.3% vs TC avg
Moderate +14% lift
Without
With
+14.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
29 currently pending
Career history
1451
Total Applications
across all art units

Statute-Specific Performance

§101
3.7%
-36.3% vs TC avg
§103
54.9%
+14.9% vs TC avg
§102
26.4%
-13.6% vs TC avg
§112
5.7%
-34.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1423 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION Election/Restrictions Applicant’s election without traverse of group II, claims 1-8, 10 in the reply filed on 5/22/26 is acknowledged. Claim 9 is withdrawn from further consideration by the examiner, 37 C.F.R. 1.142(b) as being drawn to a non-elected invention. Information Disclosure Statement The information disclosure statements filed 7/12/24; 5/22/26 have been considered. Oath/Declaration Oath/Declaration filed on 2/16/24 has been considered. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 1-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over LaVoie et al. (U.S. Patent Publication No. 2018/0308695) in view of Mohanty et al. (U.S. Patent Publication No. 2016/0329207). LaVoie et al. teaches introducing a spacer material precursor and oxygen-containing reactant and igniting a first plasma to simultaneously remove the sacrificial layer and deposit a spacer material on the exposed surfaces of the mandrel (see figure 4a-4c). However, the reference does not clearly teach depositing a sacrificial layer directly on exposed surfaces of a mandrel on a semiconductor substrate (in claim 1), the sacrificial layer is deposited conformally (in claim 4), the sacrificial layer is deposited to preferentially deposit thicker sacrificial layer material at or near the top of the mandrel than a bottom of the mandrel (in claim 5). Referring to figures 1-12, Mohanty et al. teaches a method for processing substrates, the method comprising: depositing a sacrificial layer (135) directly on exposed surfaces of a mandrel (130) on a semiconductor substrate (see paragraph# 15, figures 1-3, meeting claim 1), the sacrificial layer is deposited conformally (see figures 3, 8, meeting claim 4), the sacrificial layer is deposited to preferentially deposit thicker sacrificial layer material at or near the top of the mandrel than a bottom of the mandrel (see figures 3, meeting claim 5). Therefore, it would have been obvious to a person of ordinary skill in the requisite art at the time of the invention was filed would depositing a sacrificial layer directly on exposed surfaces of a mandrel on a semiconductor substrate in LaVoie et al. as taught by Mohanty et al. because the process is known in the art to reduce multi-patterning costs. Regarding to claim 2, the sacrificial layer comprises carbon (425, see figures 4a-4b). Regarding to claim 3, the sacrificial layer is deposited by plasma-enhanced chemical vapor deposition (see paragraph# 32). Regarding to claim 6, the sacrificial layer has a density less than a density of the mandrel (see paragraph# 53). Regarding to claim 7, the sacrificial layer has a modulus less than a modulus of the mandrel (see paragraph# 53). Regarding to claim 8, the sacrificial layer is deposited using a carbon- containing precursor (see paragraph# 32). Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Baldasseroni et al (U.S. Patent Publication No. 2018/0138036). Baldasseroni et al. teaches a method for processing substrates, the method comprising: providing a semiconductor substrate (102); depositing one or more layers of spacer material (125) on the semiconductor substrate using atomic layer deposition, wherein atomic layer deposition is performed in cycles, a cycle comprising exposing the semiconductor substrate to a deposition precursor to adsorb the deposition precursor to a surface of the substrate to form an adsorbed deposition precursor and converting the adsorbed deposition precursor to spacer material using a first plasma ignited (see paragraph# 44-45) using a plasma power of less than about 500W; and after at least one cycle atomic layer deposition, exposing the spacer material to a second plasma at a plasma energy of greater than about 25000J to form a densified spacer material (see paragraph# 57). However, the reference does not clearly teach the specific plasma power and plasma energy. In re claim 10, the specific plasma power and plasma energy is obvious because it is a matter of determining optimum process condition by routine experimentation with a limited number of species. ln re Jones, 162 USPQ 224 (CCPA 1955) (the selection of optimum ranges within prior art general conditions is obvious) and In re Boesch, 205 USPQ 215 (CCPA 1980) (discovery of optimum value of result effective variable in a known process is obvious). In such a situation, applicant must show that the particular range is critical, generally by showing that the claimed range achieves unexpected results relative to prior art range. See M.P.E.P 2144.05 III. In particular, Baldasseroni et al. suggests that the specific plasma power and plasma energy can be optimized (see tables 1-7). Therefore, it would have been obvious to a person of ordinary skill in the requisite art at the time of the invention was filed would form the spacer with specific plasma power and plasma energy in Baldasseroni et al. because choosing an optimum power and energy is known in the semiconductor art to form a conformal thickness layer. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thanh Nguyen whose telephone number is (571) 272-1695, or by Email via address Thanh.Nguyen@uspto.gov. The examiner can normally be reached on Monday-Thursday from 6:00AM to 3:30PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Yara Green, can be reached on (571) 270-3035. The fax phone number for this Group is (571) 273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pairdirect.uspto.gov. Should you have questions on access to thy Private PAIR system, contact the Electronic Business center (EBC) at 866-217-9197 (toll-free). /THANH T NGUYEN/Primary Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Feb 16, 2024
Application Filed
Aug 12, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
83%
Grant Probability
98%
With Interview (+14.3%)
2y 9m (~2m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1423 resolved cases by this examiner. Grant probability derived from career allowance rate.

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