DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Akutsu et al. (WO2018181767) (Prior Art Submitted by the applicant on 4/24/2024)
Regarding Claim 1, in Figs. 1-4, Akutsu et al. discloses a method of manufacturing a semiconductor device, comprising: preparing a carrier substrate 11/12 comprising a support 11 and a temporary fixing material layer 12 provided on the support; arranging a semiconductor chip comprising a chip main body portion CP and an electrode pad W3 provided on an outer surface of the chip main body portion on the temporary fixing material layer; forming a sealing layer 40/41 (40 is the uncured phase, 41 is the cured phase) sealing the semiconductor chip, thereby forming a sealing structure comprising the semiconductor chip and the sealing layer on the carrier substrate, the sealing structure comprising a connection (bottom)m surface in contact with the temporary fixing material layer (Figs 2C and 2D), the semiconductor chip CP being exposed to the connection (bottom) surface, and a step formed by the semiconductor chip and the sealing layer on the connection surface being 5.0 pm or less; separating the carrier substrate from the sealing structure (see Fig. 2F); and providing a redistribution layer 70 comprising multilayer wirings connected to the electrode pad and an insulating layer filling 61/62 (see Fig 3B) a space between the wirings 70 on the connection surface of the sealing structure 41.
Regarding Claim 2, in Figs. 1-4 of Akutsu et al. a thickness of the temporary fixing material layer is 50 pm or less.
Regarding Claim 3, in Figs.1-4 of Akutsu et al. a thickness of the temporary fixing material layer is more than 10 pm and 50 pm or less.
Regarding Claim 4, in Figs. 1-4 of Akutus et al. a tensile elastic modulus of the support at 23 0C is 100 GPa or more.
Regarding Claim 5, in Figs. 1-4 of Akutsu et al. the support 11 is a glass plate, a metal plate, a silicon wafer, or a ceramic plate.
Regarding Claim 6, in Figs. 1-4 of Akutsu et al, a thickness of the temporary fixing material layer and a tensile elastic modulus of the support at 23 C are selected in a range such that the step is 5.0 or less (since no more than 2 micrometer language)
Regarding Claim 7, in Figs. 1-4 of Akutsu et al, a thickness of the temporary fixing material layer is selected in a range of 50 micrometer or less.
Regarding Claim 8, in Figs. 1-4 of Akutsu et al., a thickness of the temporary fixing material layer 12 is selected in a range of more than 10 micrometer and 50 micrometer or less.
Regarding Claim 9, in Figs. 1-4 of Akutsu et al, the tensile elastic modulus of the support at 23 0C is selected in the range of 100 GPa or more.
Regarding Claim 10, in Figs. 1-4 of Akutsu et al, the support 11 is selected from a glass plate, a metal plate, a silicon wafer, and a ceramic plate.
Regarding Claim 11, in Figs. 1-4 of Akutsu et al, the insulating layer 61/62 comprises an intermediate layer interposed between the wirings and the sealing structure, and a maximum value of a thickness of the intermediate layer is 15 m or less.
Regarding Claim 12, in Figs. 1-4 of Akutsu et al, the sealing layer 40 is formed by compression molding comprising heating and pressurizing a granular sealing material comprising a curable resin and an inorganic filler in a mold.
Regarding Claim 13, in Figs. 1-4 of Akutsu et al. the sealing layer 40 is formed by a method comprising laminating a film-shaped sealing material comprising a curable resin and an inorganic filler on the carrier substrate.
Pertinent art, that is NOT relied upon on this rejection, Jang 20230223309 discloses step/level difference between top surface of the semiconductor chip and sealant.
Conclusion
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/FAZLI ERDEM/Primary Examiner, Art Unit 2812 6/20/2026
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