Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on March 4, 2024 was filed before the mailing of a first Office action on the merits. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4 and 15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 4 recites the limitation “the second direction is a direction of a connection line between the source region and the drain region,” on page 4 lines 28-29. This limitation renders the claim indefinite because when the DMOS device is turned on the connection between the source region and the drain region is not a straight line in a single direction but rather is a curved line that includes portions in depth direction through the base region and the drift region and a portion in a horizontal direction across the drift region. Thus, it is unclear which of the two directions is a second direction. For examination purposes, a second direction will be interpreted as a horizontal direction across the drift region, that is, the x-direction as shown in figs. 1A-1B.
Claim 15 recites the limitation “the second direction is a direction of a connection line between the source region and the drain region,” on page 8 lines 22-23. This limitation renders the claim indefinite because when the DMOS device is turned on the connection between the source region and the drain region is not a straight line in a single direction but rather is a curved line that includes portions in depth direction through the base region and the drift region and a portion in a horizontal direction across the drift region. Thus, it is unclear which of the two directions is a second direction. For examination purposes, a second direction will be interpreted as a horizontal direction across the drift region, that is, the x-direction as shown in figs. 1A-1B.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Schutten et al. (US 4,612,465) in view of Calafut (US 2002/0190282).
Regarding Claim 1:
Schutten discloses a trench-type Double diffusion Metal Oxide Semiconductor (DMOS) device, comprising:
a drift region with a first conduction type (n- epitaxial layer, See figs. 12-13, ref. no. 104, col. 6 lines 64-68 and col. 7 lines 1-2) and a main trench (notch, See figs. 12-13, ref. no. 118 and col. 7 lines 35-43) disposed in the drift region;
a drain region with the first conduction type (left n+ region, See fig. 13, ref. no. 140, col. 7 lines 10-22, 35-43, and col. 9 lines 18-42) and a source region with the first conduction type (right n+ region, See fig. 13, ref. no. 142, col. 7 lines 10-22, 35-43, and col. 9 lines 18-42), wherein the drain region and the source region are disposed on an upper surface of the drift region and on different sides of the main trench (the left n+ region and the right n+ region are disposed on the top surface of the n- epitaxial layer and on different side of the notch, See fig. 13, ref. nos. 118, 140, 142 and col. 7 lines 35-43);
a base region with a second conduction type (p layer, See fig. 13, ref. no. 110 and col. 7 lines 3-22 and 35-43) disposed in the drift region, the base region being in contact with and surrounding the source region (the p layer in contact with the left n+ region and surrounds the bottom and left side surface of the left n+ region, See fig. 13, ref. nos. 110, 140);
Schutten does not disclose a trench expansion gate comprising a gate insulation layer covering a bottom wall and side walls of the main trench, an expansion gate layer covering a surface of the gate insulation layer, and an insulating dielectric region covering the expansion gate layer and fully filling the main trench, wherein the expansion gate layer comprises a first expansion gate region with the second conduction type, a second expansion gate region with the first conduction type, and a third expansion gate region with the first conduction type; the second expansion gate region is disposed on a surface of the gate insulation layer on a side wall of the main trench near the source region, the third expansion gate region is disposed on a surface of the gate insulation layer on a side wall of the main trench near the drain region, and the first expansion gate region is disposed on a surface of the gate insulation layer on the bottom wall of the main trench, and extends to be adjacent to the second expansion gate region and the third expansion gate region along the surface of the gate insulation layer; an interface between the first expansion gate region and the second expansion gate region is located on a same horizontal plane as a lower boundary of the base region, or is lower than the lower boundary of the base region.
Calafut discloses a trench expansion gate (composite gate structure and gate oxide, See fig. 5, ref. nos. 311, 312, and paragraph 29) comprising a gate insulation layer (gate oxide, See fig. 5, ref. no. 312 and paragraph 29) covering a bottom wall and side walls of the main trench (the gate oxide covers the bottom wall and side walls of the trench, See fig. 5, ref. nos. 310, 312), an expansion gate layer (first portion of gate structure and second portion of gate structure, See fig. 5, ref. nos. 340, 350 and paragraphs 30-31) covering a surface of the gate insulation layer, and an insulating dielectric region (insulator covering the first portion and the second portion of the gate structure and fulling the trench such that there is no empty space in the trench, See fig. 5, ref. no. BPSG and paragraph 31) covering the expansion gate layer and fully filling the main trench, wherein the expansion gate layer comprises a first expansion gate region with the second conduction type (the first portion is formed of polysilicon doped with a p-type dopant, See fig. 5, ref. no. 340, paragraphs 30 and 36), a second expansion gate region with the first conduction type (left section of the second portion is formed of polysilicon doped with a n-type dopant, See fig. 5, ref. no. 350, paragraphs 31 and 36), and a third expansion gate region with the first conduction type (right section of the second portion is formed of polysilicon doped with a n-type dopant, See fig. 5, ref. no. 350, paragraphs 31 and 36); the second expansion gate region is disposed on a surface of the gate insulation layer on a side wall of the main trench near the source region (left section of the second portion is formed of polysilicon doped with a n-type dopant is disposed on the gate oxide near an n+ region, See fig. 5, ref. nos. 312, 330, 350), the third expansion gate region is disposed on a surface of the gate insulation layer on a side wall of the main trench near the drain region (right section of the second portion is formed of polysilicon doped with a n-type dopant is disposed on the gate oxide near an n+ region, See fig. 5, ref. nos. 312, 330, 350), and the first expansion gate region is disposed on a surface of the gate insulation layer on the bottom wall of the main trench (the first portion is formed of polysilicon doped with a p-type dopant is disposed on the gate oxide on the bottom wall of the trench, See fig. 5, ref. nos. 310, 312, 340), and extends to be adjacent to the second expansion gate region and the third expansion gate region along the surface of the gate insulation layer (the first portion is in contact with the left section of the second portion and the right section of the second portion along the gate oxide, See fig. 5, ref. nos. 312, 340, 350); an interface between the first expansion gate region and the second expansion gate region is located on a same horizontal plane as a lower boundary of the base region (an interface between the first portion and the left section of the second portion is located on a same horizontal plane as a lower boundary of the p-type channel region and the p-type body region, See fig. 5, ref. nos. 305, 332, 340, 350 and paragraphs 28-31), or is lower than the lower boundary of the base region.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the field effect transistor of Schutten to include a trench expansion gate comprising a gate insulation layer covering a bottom wall and side walls of the main trench, an expansion gate layer covering a surface of the gate insulation layer, and an insulating dielectric region covering the expansion gate layer and fully filling the main trench, wherein the expansion gate layer comprises a first expansion gate region with the second conduction type, a second expansion gate region with the first conduction type, and a third expansion gate region with the first conduction type; the second expansion gate region is disposed on a surface of the gate insulation layer on a side wall of the main trench near the source region, the third expansion gate region is disposed on a surface of the gate insulation layer on a side wall of the main trench near the drain region, and the first expansion gate region is disposed on a surface of the gate insulation layer on the bottom wall of the main trench, and extends to be adjacent to the second expansion gate region and the third expansion gate region along the surface of the gate insulation layer; an interface between the first expansion gate region and the second expansion gate region is located on a same horizontal plane as a lower boundary of the base region as taught by Calafut in order to improve the gate structure of the field effect transistor. (See Calafut abstract.)
Regarding Claim 8:
Calafut discloses wherein the first expansion gate region is polycrystalline silicon with the second conduction type (the first portion is formed of polysilicon doped with a p-type dopant, See fig. 5, ref. no. 340, paragraphs 30 and 36), and the second expansion gate region and the third expansion gate region are polycrystalline silicon with the first conduction type (the left section and the right section of the second portion is formed of polysilicon doped with a n-type dopant, See fig. 5, ref. no. 350, paragraphs 31 and 36).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Schutten et al. (US 4,612,465) in view of Calafut (US 2002/0190282) further in view of Lee et al. (US 5,122,848)
Regarding Claim 7:
The above stated combination of Schutten and Calafut discloses the above stated trench-type DMOS device.
The above stated combination of Schutten and Calafut does not disclose wherein a thickness of the expansion gate layer ranges from 1000 to 3000 angstroms.
Lee discloses a thin gate polysilicon layer deposited to a thickness of about 500 to 1000 Angstroms (See fig. 3, ref. no. 24 and col. 3 lines 42-62).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the field effect transistor of Schutten and Calafut to include a thin gate polysilicon layer deposited to a thickness of about 500 to 1000 Angstroms as taught by Lee in order to make the field effect transistor thinner for lower voltage applications.
Allowable Subject Matter
Claims 2-3 and 5-6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim 4 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims. Claims 9-14 and 16-17 are allowable. Claim 15, upon being rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action, would be allowable due to its dependency on independent claim 9.
The following is a statement of reasons for the indication of allowable subject matter: with respect to dependent claim 2, the disclosures and illustrations of Schutten and Calafut as discussed above fail to teach and/or suggest a secondary trench, wherein the secondary trench is located in the drift region, and is in communication with the main trench, and the secondary trench is provided with the second expansion gate region, and a fourth expansion gate region with the second conduction type connected to the second expansion gate region. Further, the prior art also fails to provide other relevant disclosures which are properly combinable with Schutten and Calafut to teach and/or suggest the limitations of claim 2. Claims 3-5 depend from claim 2, and thus, include the subject matter of claim 2. Therefore, claims 2-5 include allowable subject matter.
With respect to dependent claim 6, the disclosures and illustrations of Schutten and Calafut as discussed above fail to teach and/or suggest a secondary trench, wherein a length of the second expansion gate region in a third direction ranges from 3000 to 5000 angstroms, or a length of the third expansion gate region in the third direction ranges from 2000 to 6000 angstroms, and the third direction is a direction perpendicular to the upper surface of the drift region. Further, the prior art also fails to provide other relevant disclosures which are properly combinable with Schutten and Calafut to teach and/or suggest the limitations of claim 6. Therefore, claim 6 includes allowable subject matter.
With respect to independent claim 9, the disclosures and illustrations of Calafut disclose a method of manufacturing a trench-type DMOS device, comprising:
providing a drift region with a main trench (forming a trench in an n-epitaxial layer, See fig. 5, ref. nos. 310, 325 and paragraphs 28-29), wherein the drift region is of a first conduction type;
forming a gate insulation layer (depositing a gate oxide on the bottom wall and side walls of the trench, See fig. 5, ref. no. 312 and paragraph 29) on a bottom wall and side walls of the main trench;
forming a first expansion gate region (forming a first portion of polysilicon doped with a p-type dopant on the gate oxide, See fig. 5, ref. no. 312, 340, paragraphs 30 and 36) with a second conduction type on a surface of the gate insulation layer;
forming a second expansion gate region (forming a left section of a second portion of polysilicon doped with a n-type dopant, See fig. 5, ref. no. 350, paragraphs 31 and 36) and a third expansion gate region (forming a right section of a second portion of polysilicon doped with a n-type dopant, See fig. 5, ref. no. 350, paragraphs 31 and 36) on the upper surface of the first expansion gate region, wherein the second expansion gate region and the third expansion gate region are located on different sides of the insulating dielectric region (the left section of the second portion and the right second of the second portion are formed on opposite side of an insulator, See fig. 5, ref. nos. BPSG, 350, and paragraph 31) and are in contact with the insulating dielectric region (the left section of the second portion and the right second of the second portion are in contact with the insulator through the conformal polycide layer, See fig. 5, ref. nos. BPSG, 345, 350, and paragraph 31), and the second expansion gate region and the third expansion gate region are of the first conduction type (the left section of the second portion and the right second of the second portion n-type, See fig. 5, ref. nos. 350, paragraphs 31 and 36);
forming a base region with the second conduction type (forming p-type channel region and a p-type body region on an upper surface of the n- epitaxial layer, See fig. 5, ref. nos. 305, 332, 340, 350 and paragraphs 28-31) on an upper surface of the drift region near the second expansion gate region, wherein a lower boundary of the base region is located on a same horizontal plane as a lower boundary of the second expansion gate region (a lower boundary of the p-type channel region and the p-type body region is located on a same horizontal plane as the lower boundary of the left section of the second portion, See fig. 5, ref. nos. 305, 332 332, 340, 350 and paragraphs 28-31), or the lower boundary of the base region is higher than the lower boundary of the second expansion gate region;
forming a source region (implanting the left n+ region p-type channel region and a p-type body region, See fig. 5, ref. no. 330 and paragraph 29) with the first conduction type on an upper surface of the base region.
Calafut fails to teach and/or suggest forming an insulating dielectric region on a surface of the first expansion gate region and fully filling the main trench with the insulating dielectric region, wherein an upper surface of the gate insulation layer between the insulating dielectric region and the side walls of the main trench and an upper surface of the first expansion gate region are exposed through a trench opening of the main trench, and the first expansion gate region is exposed on both sides of the insulating dielectric region and forming a drain region with the first conduction type on an upper surface of the drift region near the third expansion gate region. The prior art also fails to provide other relevant disclosures which are properly combinable with Calafut to teach and/or suggest these limitations of claim 9. Claims 10-17 depend from claim 9, and thus, include the subject matter of claim 9. Therefore, claims 9-17 are allowable.
Conclusion
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/CALEEN O SULLIVAN/Primary Examiner, Art Unit 2899
/B.S./Examiner, Art Unit 2899
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