DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-8 in the reply filed on 07/20/2026 is acknowledged.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-4 and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kiritani (US 2002/0052102) in view of Sasaki et al (US 2023/0227979).
Kiritani teaches a single crystal 4H-SiC substrate 1 having a blanket oxide film having a thickness of 20 nm is formed on the surface of the substrate by a thermal oxidation process ([0004]-[0040]; Fig 4A), which clearly suggests a protective oxide on a first face of a silicon carbide disk.
Kirtani does not explicitly teach the protective oxide is characterized by having a thickness variation along the covered area that is less than a predetermined tolerance value from a mean thickness.
In a method of making oxide layer, Sasaki et al teaches a film thickness variation of an oxide film formed on a wafer is +0.4%; and other embodiments where the film thickness of the formed oxide film also varies within ±0.6% or within +1.0% ([0066], [0071]-[0072], [0080]; Fig 7B). Sasaki et al also teaches the method of deposition may be suitably applied to oxidation of silicon-based substrates such as Si, SiC, and SiGe, and may also be widely applied to deposition of films such as metal oxide films for which an oxidizing precursor is used ([0084])
It would have been obvious to one of ordinary skill in the art at the time of filing to modify Kirtani by making an oxide layer having a uniform film thickness of +0.4%, as taught by Sasaki et al, to form a uniform oxide layer having uniform properties across the surface of the wafer.
Referring to claim 2, the combination of Kiritani and Sasaki et al teaches a 20 nm thick oxide with a thickness variation of less than +1.0%, which clearly suggests a mean thickness of 20 nm.
Referring to claim 3, the combination of Kiritani and Sasaki et al teaches a 20 nm thick oxide with a thickness variation of less than +1.0%, which clearly suggests a mean thickness of 20 nm and a tolerance of less than 0.5 nm.
Referring to claim 4, the combination of Kiritani and Sasaki et al teaches a 20 nm thick oxide with a thickness variation of less than +1.0%, which clearly suggests a deviation of not more than 0.3 nm from the mean thickness.
Referring to claim 7, the combination of Kiritani and Sasaki et al teaches 4H-SiC (Kiritani ([0004]-[0040]; Fig 4A).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kiritani (US 2002/0052102) in view of Sasaki et al (US 2023/0227979), as applied to claims 1-4 above, and further in view of Kido et al (US 2021/0047750).
The combination of Kiritani and Sasaki et al teaches all of the limitations of claim 5, as discussed above, except the monocrystalline silicon carbide disk has a thickness between 500 mm and 5000 mm; and/or a diameter greater than or equal to 150 mm.
In a method of making a SiC seed crystal, Kido et al teaches a disk-shaped seed crystal for single crystal 4H-SiC growth having a diameter of more than 150 mm and having a thickness within a range of more than or equal to 1 mm and less than or equal to 0.03 times of the diameter ([0024], [0033]-[0037], [0061]). Kido et al teaches It is desirable to increase the diameter of a single crystal SiC substrate to reduce process cost, and currently, a single crystal SiC substrate having a diameter of 150 mm is commercially available ([0061]).
It would have been obvious to one of ordinary skill in the art at the time of filing to modify the combination of Kiritani and Sasaki et al by using a monocrystalline silicon carbide disk has a thickness between 500 mm and 5000 mm; and/or a diameter greater than or equal to 150 mm, as taught by Kido et al, because changes in size and shape are prima facie obvious (MPEP 2144.04), larger crystals are desirable to reduce process costs, and seed crystals with the claimed size are commercially available.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kiritani (US 2002/0052102) in view of Sasaki et al (US 2023/0227979), as applied to claims 1-4 above, and further in view of Yabuki et al (US 2021/0375613).
The combination of Kiritani and Sasaki et al teaches all of the limitations of claim 6, as discussed above, except the first face of the monocrystalline silicon carbide disk has a surface roughness between 0.5 nm and 1 nm in the direction of the monocrystalline silicon carbide disk thickness.
In a method of making SiC seed crystals, Yabuki et al teaches an SiC wafer 40 (monocrystalline 4H or 6H SiC substrate) and a surface roughness of the SiC wafer 40 is reduced by polishing, and the surface of the post-polishing wafer has an arithmetic surface roughness (Ra) of 0.7 nm or less, and an explicit example of the surface roughness after the polishing step was 0.64 nm ([0009], [0025], [0041], [0058]). Yabuki et al teaches a lower surface roughness after the polishing step makes scratches less likely to occur ([0060]).
It would have been obvious to one of ordinary skill in the art at the time of filing to modify the combination of Kiritani and Sasaki et al by using a monocrystalline silicon carbide disk that has a surface roughness between 0.5 nm and 1 nm in the direction of the monocrystalline silicon carbide disk thickness, as taught by Yabuki et al, because a polished seed has reduced roughness for producing smoother layers thereon, and a reduce roughness reduces scratches.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kiritani (US 2002/0052102) in view of Sasaki et al (US 2023/0227979), as applied to claims 1-4 above, and further in view of Kamata et al (US 2021/0108334).
The combination of Kiritani and Sasaki et al teaches all of the limitations of claim 8, as discussed above, except etch pit density of less than 12000/cm2 and/or a screw dislocation density of less than 2000/cm2.
In a method of making a single crystal SiC wafer, Kamata et al teaches a silicon carbide single crystal wafer manufactured by a gas growth technique has a screw dislocation density of 500 dislocations/ cm2 or less; and etch pit density of the wafer is 3500 dislocations/ cm2 or less (abstract; [0026], [0037], [0086]-[0090]). Overlapping ranges are prima facie obvious (MPEP 2144.05).
It would have been obvious to one of ordinary skill in the art at the time of filing to modify the combination of Kiritani and Sasaki et al by using a SiC seed having an etch pit density of less than 12000/cm2 and/or a screw dislocation density of less than 2000/cm2, as taught by Kamata et al, because few defects are desirable to produce higher quality devices.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Ishibashi (US 2015/0325637) teaches a single crystal silicon carbide substrate with an average value of surface roughness Ra at front surface 11 is not greater than 0.5 nm and an average value of surface roughness Ra at back surface 12 is not smaller than 0.3 nm and not greater than 10 nm a, and diameter D of front surface 11 is not smaller than 110 mm ([0068]).
JP 2014-086711 teaches a SiC substrate and a gate oxide film generally needs to have a thickness of 50 to 100 nm and the non-uniformity of the oxide film with respect to the entire film thickness is 1.5% to 3.0% (Computer translation [0061]).
Gao et al (US 2012/0122715) teaches 4 in Si wafers coated with 500 nm SiO2 and by ellipsometric measurements, it was determined that there was only <0.5 nm variation in the SiO2 layer thickness over the entire 4 in. substrate ([0094], FIG. 4).
JP 06-053223 teaches it is necessary to have a process for controlling the film thickness variation of the extremely thin silicon oxide film of 10 nm or less to a minimum, for example, within ± 0.2 nm and in addition to controlling the film thickness uniformity on the surface of each semiconductor substrate, it is also necessary to control the film thickness uniformity over the entire semiconductor substrate mounted on the boat (Computer translation [0006]).
JP 2005-116896 teaches a SiC substrate; final polishing may be performed up to 1 nm or less; and forming a thermal oxide film 2 having a thickness of. When the thickness of the thermal oxide film 2 is 2 nm or more and 10 nm or less; and the difference in the unevenness on the upper surface of the gate insulating film becomes 0.5 nm or less by using a planarization treatment to flatten the upper surface of the silicon carbide layer using the CMP method (Computer translation [0019]-[0020], [0034]-[0035])
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MATTHEW J. SONG
Examiner
Art Unit 1714
/MATTHEW J SONG/Primary Examiner, Art Unit 1714
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