Prosecution Insights
Last updated: July 17, 2026
Application No. 18/691,546

DISPLAY DEVICE

Non-Final OA §103§112
Filed
Mar 13, 2024
Priority
Dec 07, 2021 — nonprovisional of PCTJP2021044808
Examiner
GOODWIN, DAVID J
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Sharp Display Technology Corporation
OA Round
1 (Non-Final)
67%
Grant Probability
Favorable
1-2
OA Rounds
10m
Est. Remaining
84%
With Interview

Examiner Intelligence

Grants 67% — above average
67%
Career Allowance Rate
547 granted / 813 resolved
-0.7% vs TC avg
Strong +17% interview lift
Without
With
+16.6%
Interview Lift
resolved cases with interview
Typical timeline
3y 2m
Avg Prosecution
56 currently pending
Career history
889
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
82.7%
+42.7% vs TC avg
§102
3.0%
-37.0% vs TC avg
§112
10.4%
-29.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 813 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The information disclosure statement (IDS) submitted on 3/13/2024 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Objections Claim 5 is objected to because of the following informalities: Claim 5 recites “each of date signal wirings” in line 2. The grammar is incorrect, examiner suggests “each data signal wiring”. Appropriate correction is required. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1 through 9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 1 recites the limitation "the plurality of scanning signals" in line 12. There is insufficient antecedent basis for this limitation in the claim. The examiner suggests “the plurality of scanning signal wirings” Claim 5 recites “a routed wiring portion” in lines 2 and 3. It is unclear whether this refers to “a routed wiring portion recited in claim 1 line 10. Claims 2, 3, 4, 6, 7 8 9 are rejected as being dependent on and incorporating claim 1. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Rejection Note: Italicized and struck through claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s). Claim(s) 1 through 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi (US 2017/0162637) in view of Koide (US 2022/0019306). Regarding claim 1. Choi teaches A display device (fig 1,2:1; [para 0067]) having a display area (fig 2:DA; [para 0076]) including: a plurality of scanning signal wirings (fig 2,3a:SLi; [para 0080]); a plurality of data signal wirings (fig 2,3a:DLj; [para 0081]) intersecting with the plurality of scanning signal wirings (fig 2,3a:SLi; [para 0080]); and a plurality of subpixel circuits (fig 1:PX; [para 0067]) each disposed to a corresponding one of a plurality of intersections of the plurality of scanning signal wirings (fig 2,3a:SLi; [para 0080]) and the plurality of data signal wirings (fig 2,3aDLj; [para 0081]), the display device (fig 1,2:1; [para 0067]) comprising a first region (fig 2,3a:TH; [para 0077]) and a second region (fig 2,3a:NA1; [para 0079]) not provided with the plurality of subpixel circuits (fig 1:PX; [para 0067]), the first region (fig 2,3a:TH; [para 0077]) being surrounded with the second region (fig 2,3a:NA1; [para 0079]) and the second region (fig 2,3a:NA1; [para 0079]) being surrounded with the display area (fig 2:DA; [para 0076]), wherein, when viewed in a direction (fig 2,4:3rd direction) perpendicular to the display area (fig 2:DA; [para 0076]), each of a plurality of signal wirings (fig 2,3a:SLi; [para 0080]) includes a routed wiring portion that bypasses the first region (fig 2,3a:TH; [para 0077]) and passes through the second region (fig 2,3a:NA1; [para 0079]), the plurality of signal wirings (fig 2,3a:SLi; [para 0080]) at least including: scanning signal wirings included in the plurality of scanning signals; or data signal wirings (fig 2,3aDLj; [para 0081]) included in the plurality of data signal wirings (fig 2,3aDLj; [para 0081]), and the display device (fig 1,2:1; [para 0067]) comprises a portion of the routed wiring portion in a width direction (fig 3a:1st direction; [para 0088]), and formed to overlap with another portion of the routed wiring portion in the width direction (fig 3a:1st direction; [para 0088]). PNG media_image1.png 380 653 media_image1.png Greyscale Choi does not teach a dummy contact hole. Koide teaches: the display device (fig 2:PNL; [para 0026]) comprises a dummy contact hole (fig 6:CHD; [para 0070]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a dummy contact hole between wirings in order to reduce parasitic capacitance between signal lines (paragraph 4). Regarding claim 2. Choi in view of Koide teaches the display device according to claim 1, further Choi teaches: the routed wiring portion so that the portion of the routed wiring portion in the width direction is left on opposing sides . Koide teaches the dummy contact hole (fig 6:CHD; [para 0070]) is formed into a slit (fig 6:SPL; [para 0089]) along the wiring portion (fig 6:TLG1-2; [para 0062]) so that the portion of the wiring portion (fig 6:TLG1-2; [para 0062]) in the width direction is left on opposing sides of the dummy contact hole (fig 6:CHD; [para 0070]). PNG media_image2.png 621 808 media_image2.png Greyscale Regarding claim 3. Choi in view of Koide teaches the display device according to claim 1, further Choi teaches: an end of the routed wiring portion in the width direction. Koide teaches: the dummy contact hole (fig 6:CHD; [para 0070]) is formed to overlap with an end of the wiring portion (fig 6:TLG1-2; [para 0062]) in the width direction (fig 6:X; [para 0027]). Regarding claim 4. Choi in view of Koide teaches the display device according to claim 1, further Choi teaches: a longitudinal direction (fig 2,3a:2nd direction; [para 0089]) of the plurality of signal wirings (fig 2,3a:DLj; [para 0081]) with respect to the first region (fig 2,3a:TH; [para 0077]). Koide teaches: the dummy contact hole (fig 6:CHD; [para 0070]) is disposed perpendicularly (fig 6:Z; [para 0027]) to a longitudinal direction (fig 6:Y; [para 0027]) of the plurality of signal wirings (fig 6:TLG1-2; [para 0062]). Regarding claim 5. Choi in view of Koide teaches the display device according to claim 1, further Choi teaches: each of data signal wirings included in the plurality of data signal wirings (fig 2,3a:DLj; [para 0081]) includes a routed wiring portion that bypasses the first region (fig 2,3a:TH; [para 0077]) and passes through the second region (fig 2,3a:NA1; [para 0079]), and first scanning signal wirings of the scanning signal wirings included in the plurality of the scanning signal wirings (fig 2,3a:SLi; [para 0080]) are connected to one (fig 2,3a:20; [para 0070]) of a pair of gate drivers (fig 2,3a:20,30; [para 0070]) arranged at opposing sides of the display area (fig 2:DA; [para 0076]), and second scanning signal wirings of the scanning signal wirings included in the plurality of the scanning signal wirings (fig 2,3a:SLi; [para 0080]) are connected to another one (fig 2,3a:30; [para 0070]) of the pair of gate drivers (fig 2,3a:20,30; [para 0070]). Regarding claim 6. Choi in view of Koide teaches the display device according to claim 1, further Choi teaches: the first region (fig 2,3a:TH; [para 0077]) is provided with a camera hole for imaging (fig 17a; [para 0173]). Regarding claim 7. Choi in view of Koide teaches the display device according to claim 1, further Choi teaches: a spacing between routed wiring portions adjacent to one another and passing through the second region (fig 2,3a:NA1; [para 0079]) is narrower than a spacing between the signal wirings (fig 2,3aDLj; [para 0081]) adjacent to one another and passing through the display area (fig 2:DA; [para 0076]), the routed wiring portions being included in the routed wiring portion. PNG media_image3.png 463 654 media_image3.png Greyscale Regarding claim 8. Choi in view of Koide teaches the display device according to claim 1, further Choi teaches: each of the plurality of subpixel circuits (fig 1:PX; [para 0067]) includes: a control circuit including a transistor (fig 6:T1; [para 0106]); a reflective electrode (fig 6:121; [para 0120]); a light-emitting element (fig 6:122; [para 0121]); and a transparent electrode (fig 6:123; [para 0122]). Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi (US 2017/0162637) in view of Koide (US 2022/0019306) as applied to claim 1 and further in view of Xu (US 2022/0181357) Regarding claim 9. Choi in view of Koide teaches the display device according to claim 1, further Choi teaches: the scanning signal wirings (fig 2,3a:SLi; [para 0080]) . Choi in view of Koide does not teach the scanning signal wirings are in the routed wiring portion. Xu teaches: each of the scanning signal wirings (fig 6:1351,1353; [para 0035]) included in the plurality of scanning signal wirings (fig 6:135; [para 0035]) includes the routed wiring portion (fig 6,7:1352; [para 0035]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the scanning signal wirings to included the routed wiring portion so that the scanning signal wirings can bypass the camera hole (paragraph 6). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID J GOODWIN whose telephone number is (571)272-8451. The examiner can normally be reached Monday - Friday, 11:00 - 19:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571)272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /D.J.G/Examiner, Art Unit 2817 /Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
Read full office action

Prosecution Timeline

Mar 13, 2024
Application Filed
Jun 04, 2026
Non-Final Rejection mailed — §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
67%
Grant Probability
84%
With Interview (+16.6%)
3y 2m (~10m remaining)
Median Time to Grant
Low
PTA Risk
Based on 813 resolved cases by this examiner. Grant probability derived from career allowance rate.

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