DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 06/03/2026 have been fully considered but they are not persuasive.
The claim objections of record are withdrawn in light of applicant’s amendments.
The USC 102 rejections of record are withdrawn in light of applicant’s amendments.
Applicant’s arguments with respect to amended claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 8-11, and 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over US 2014/0310670 A1 [herein after Oberai] in view of US 2019/0086340 A1 [hereinafter Leu].
Regarding Claims 1, 15 and 20:
Oberai teaches:
a system for identifying a failure mechanism (para. [0007]: “a computer system for defect characterization”), the system comprising a controller including circuitry configured to cause the system to perform (para. [0091]: “a programmable apparatus which executes any of the above mentioned computer program products or computer-implemented methods may include one or more microprocessors, microcontrollers, embedded microcontrollers...”):
a non-transitory computer readable medium that stores a set of instructions that is executable by at least one processor of a computing device to cause the computing device to perform a method for classifying and identifying failure mechanisms (para. [0007]: “a computer program product embodied in a non-transitory computer readable medium for defect characterization”), the method comprising:
a method for identifying a failure mechanism (para. [0005]: “A computer implemented method for defect characterization”, the method comprising:
analyzing a first plurality of voltage contrast images of a sample to identify a plurality of defects (paras. [0034-0036]: “obtaining images 120 of a semiconductor chip which comprises the semiconductor circuit during fabrication... The images may emphasize one or more defects using voltage contrast... detecting a defect 130 in one of the images of the semiconductor chip... Detection of the defect may be accomplished by software inspection of the images”); and
analyzing a pattern of a subset of the plurality of defects to determine a failure mechanism for the subset of the plurality of defects (paras. [0051- 0055]: Oberai distinguishes systematic defects from random defects and states systematic defects are found “with high frequency near some similar layout arrangement” (“a pattern of a subset of the plurality of defects”); Oberai also describes searching the layout for geometries similar to the area where a defect was detected and detecting additional defects at those similar geometries, and performing failure analysis to determine “root cause” of failure (“failure mechanism”)),
However, Oberai does not specially note that wherein the pattern of the subset of the plurality of defects comprises a spatial relationship among the subset of the plurality of defects within the voltage contrast images relative to one another.
Leu teaches wherein the pattern of the subset of the plurality of defects comprises a spatial relationship among the subset of the plurality of defects within the voltage contrast images relative to one another (paras. [0013, 0057]: “defect image 1101 of image file 1001…Include defect contour image 1101 and its coordinate location relative to surrounding circuit pattern,” retrieving “the defect image pattern and its surrounding pattern based on the defect image's coordinate location”, “perform pattern match based on the original defect image 1101 contour and defect layout pattern. Judge whether this original defect image contour is an open circuit failure type failure defect or short circuit failure type failure defect”).
Therefore, it would have been obvious for an ordinary skilled person in the art, before the effective time of filing, to modify Oberai’s defect characterization system to use Leu’s coordinate-based defect-pattern mapping because both references are directed to semiconductor defect inspection using defect images and layout/design information, and thus using Leu’s defect contour/coordinate mapping and Critical Areas analysis in Oberai’s failure-analysis workflow would improve identification of systematic, yield-impacting failure mechanism,, such as open-circuit and short-circuit defects, and to reduce incorrect critical/non-critical defect judgment.
Regarding Claims 2 and 16:
Oberai in view of Leu teach the system of claim 1 and the non-transitory computer readable medium of claim 15, respectively. Oberai further teaches wherein the controller includes circuitry configured to cause the system to further perform:
analyzing a correlation between the pattern of the subset of the plurality of defects and a plurality of layout designs associated with the sample to facilitate determination of the failure mechanism (paras. [0027-0029, 0032]: teaches “correlating a defect of interest to the layout and netlist,” and states that defects can be classified and filtered based on circuit impact, such that defects can be binned together (a “design-based binning” process), separating systematic defects from random defects).
Regarding Claims 3 and 17:
Oberai in view of Leu teach the system of claim 1 and the non-transitory computer readable medium of claim 15, respectively. Oberai further teaches wherein the controller includes circuitry configured to cause the system to further perform:
analyzing the pattern of the subset of the plurality of defects to determine a classification for the subset of the defects (paras. [0032, 0041]: separating “systematic defects from random defects... to perform inline defect classification”, that “classification may include whether a defect is a short, resistive short, a capacitive link...the layer where the defect came during fabrication... the material of the defect... whether the defect is systematic or s random defect”).
Regarding Claims 4 and 18:
Oberai in view of Leu teach the system of claim 3 and the non-transitory computer readable medium of claim 17, respectively.
Leu further teaches:
generating [defect images] based on a plurality of perturbation simulations (Fig. 7D and para. [0056]: (part of Step 150 in Fig. 2 flowchart) perform Monte-Carlo simulations to generate defect data includes artificially injected defect, demonstrated as defect images 1101 as shown in fig. 7D),
wherein the [defect images] comprise a plurality of patterns (Fig. 7D and paras. [0055-0056]: each defect image 1101 includes defect layout pattern 1111 which is related to a circuit layout 1113); and
comparing the [defect images] and determining a plurality of correlations between the plurality of perturbation simulations and the plurality of patterns (para. [0064]: (part of Step 170 in Fig. 2 flowchart) perform defect classification for defect images 1101, i.e., matching defect image pattern and mapped layout pattern to classify defect type, thus, the classified defect pattern is associated with the corresponding artificially generated (simulated) defect condition).
Although Leu does not expressly use the term “classifier,” Leu teaches a “data processing center 21” that perform the defect-analysis and classification operations in the Fig. 2 workflow. Accordingly, one or more processors of the data processing center 21 would inherently be implemented as classifier for defect classification.
As such, modifying Oberai in view of Leu would implement the perturbation simulation and classification techniques of Leu to classify the voltage contrast images obtained in Leu for defect analysis.
Regarding Claims 5 and 19:
Oberai in view of Leu teaches the system of claim 4 and the non-transitory computer readable medium of claim 18, respectively. Oberai further teaches perform the plurality of perturbation simulations (para. [0049]: a simulation engine 460 analyzes the netlist 422 to detect defects) by:
selecting a plurality of layout designs, wherein the plurality of layout designs comprises a plurality of features of a sample (para. [0050]: “importing a layout 500 for a semiconductor circuit… for describing various shapes, sizes, and relationships of elements in a semiconductor layout”); and
defining a conductive path in the plurality of layout designs (paras. [0034, 0042, 0050]: teaches importing a netlist, extracting and identifying nets (including intersections of nets), and cross-mapping between layout and netlist, thereby defining electrical connectivity (“conductive paths”) within the selected layout for subsequent electrical analysis).
Regarding Claim 6:
Oberai in view of Leu teaches the system of claim 4. Leu further teaches wherein the plurality of perturbation simulations comprises a plurality of simulated patterning steps during processing of a sample (para. [0056]: during the Monte Carlo simulation, “randomly generated defect data are spread randomly over different coordinate location in a full chip design layout”, effectively forming defect patterns on the sample layout during simulation).
Regarding Claim 8:
Oberai in view of Leu teaches the system of claim 4. Leu further teaches wherein each pattern of the plurality of patterns comprises a layout of features on a sample (paras. [0037, 0053]: “defect image pattern 1101 is created in design layout pattern 1110 file,” which “include plurality of layout pattern (i.e. device layout pattern) …includes layout pattern geometry size, layout pattern coordinate, layout pattern layer, text mark or dimension”).
Regarding Claim 9:
Oberai in view of Leu teaches the system of claim 4. Oberai further teaches wherein the failure mechanism comprises a plurality of root causes of a defect in a sample (para. [0055]: “Failure analysis can include evaluation of failing semiconductor devices to determine root cause of failure through examination of the structures and defects on a physical device”).
Regarding Claim 10:
Oberai in view of Leu teaches the system of claim 9. Oberai further teaches wherein the defect is within a layer of the sample (paras. [0037, 0041 and 0043]: “filtering out defects based on size 132, where the defect is smaller than the critical dimension for a defect which could affect a single layer in the manufacturing process,” also “Classification may include the layer where the defect came from during the fabrication process”).
Regarding Claim 11:
Oberai in view of Leu teaches the system of claim 1. Oberai further teaches wherein the pattern of the subset of the plurality of defects of the first plurality of voltage contrast images comprises a repeating pattern of features (para. [0043]: teaches searching layout for similar geometries/a specific geometric pattern occurring at multiple locations and detecting additional defects at those similar geometries (“a repeating pattern of features”)).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Oberai in view of Leu, further in view of US 2016/0291198 A1 [hereinafter Lee].
Regarding Claim 7:
Oberai in view of Leu teaches the system of claim 4. However, the combined references does not specifically note that wherein the plurality of perturbation simulations comprises a plurality of materials used during processing of a sample. Lee teaches wherein the plurality of perturbation simulations comprises a plurality of materials used during processing of a sample (para. [0026]: “FIG. 2 is an illustrative graph showing a Monte Carlo simulation of the backscattered photons …While maintaining the same geometry, as shown in FIG. 1, the defect material was changed to air, water, and cement”).
Therefore, it would have been obvious for an ordinary skilled person in the art, before the effective time of filing, to apply Lee’s material- variation Monte Carlo simulation approach to the perturbation simulation used in the combined Oberai and Leu defect classification workflow, so that the Oberai and Leu’s simulation set would include multiple material conditions. One of ordinary skilled in the art would be motivated to do so since as explained in Lee, with geometry held constant, changing material in simulation changes the resulting response/signature, demonstrating that material variation is a meaningful simulation parameter and applying the material-variation simulation would improve robustness of defect pattern classification across different material related defect conditions.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Oberai in view of Leu, further in view of US 2019/0189457A1 [hereinafter Lie].
Regarding Claim 12:
Oberai in view of Leu teaches the system of claim 11. However, Oberai does not specifically note that wherein the failure mechanism for the subset of the plurality of defects comprises pitch walking due to any one of self-aligned double patterning or self-aligned quadruple patterning of a sample. Lie teaches wherein the failure mechanism for the subset of the plurality of defects comprises pitch walking due to any one of self-aligned double patterning or self-aligned quadruple patterning of a sample (para. [0032]: “One or more embodiments advantageously employ …SADP (Self-Aligned Double Patterning) …With 2 color SADP, meaning two mandrel lithography steps, the overlay could cause “pitch walking” (wherein the Fin-to-Fin distances are not equal) in the Fin structure”).
Lie teaches pitch-walking, a specific patterning-related failure in semiconductor fabrication, and explains the physical manifestation of such failures. Therefore, it would have been obvious for an ordinary skilled person in the art, before the effective time of filing, to add Lie’s specific pitch-walking failure mechanism to Oberai’s defect/failure mechanism. One of ordinary skilled in the art would be motivated to do so because as Lie explained that pitch walking is a known overlay-induced defect mechanism in self-aligned patterning, thus incorporating this known, process-specific mechanism into Oberai’s broader defect/failure mechanism would have predictably improved the specificity and accuracy of failure mechanism identification for patterning-related defects in semiconductor structures.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Oberai in view of Leu, further in view of US 10276346 B1[hereinafter Duffy].
Regarding Claim 13:
Oberai in view of Leu teach the system of claim 1. However, Oberai does not specifically note that wherein the pattern of the subset of the plurality of defects of the first plurality of voltage contrast images comprises a checkerboard of features. Duffy teaches wherein the pattern of the subset of the plurality of defects of the first plurality of voltage contrast images comprises a checkerboard of features (Figs. 3B -3C and 15:31-34: “structures of a voltage contract image may typically exhibit a range of grayscale values based on various factors including electrical connectivity to ground…”, i.e., checkerboard features, as the grayscale alternating patterns shown in Figs. 3B and 3C.
Therefore, it would have been obvious for an ordinary skilled person in the art, before the effective time of filing, to add Duffy’s voltage-contrast pattern with checkboard features to Oberai’s voltage-contrast defect analysis. One of ordinary skilled in the art would be motivated to do so since both Oberai and Duffy use voltage contrast image for their defect analysis, and Duffy explains the voltage contrast image appearance (including the alternating grayscale feature patterns) is driven by electrical connectivity condition. As such, such an incorporation would have been a predictable use of known voltage contrast image pattern behavior to improve classification of specific defect-pattern types in semiconductor inspection images.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Oberai in view of Leu and Duffy, further in view of US 2004/0169861A1 [hereinafter Mieher].
Regarding Claim 14:
Oberai in view of Leu and Duffy teaches the system of claim 13. However, the combined references do not specifically note that wherein the failure mechanism for the subset of the plurality of defects comprises an overlay defect between a plurality of layers of a sample. Mieher teaches wherein the failure mechanism for the subset of the plurality of defects comprises an overlay defect between a plurality of layers of a sample (Abstract: “determining overlay error between two layers of a sample”).
Therefore, it would have been obvious for an ordinary skilled person in the art, before the effective time of filing, to add Mieher’s inter-layer overlay error detection to the combined Oberai and Duffy defect/failure mechanism analysis. One of ordinary skilled in the art would be motivated to do so since interlayer overlay error is a known semiconductor fabrication defect mechanism, that is specifically measurable between layers, and Oberai teaches “identify geometric pattern for one or more layers where defects may occur”. Therefore, including overlay defect failure mechanism would have been a predictable use of a known semiconductor defect mechanism to improve the ability of the combined system to identify defects associated with layer-to-layer misalignment.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JING WANG whose telephone number is (571)272-2504. The examiner can normally be reached M-F 7:30-17:00.
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/JING WANG/Examiner, Art Unit 2881
/DAVID E SMITH/Examiner, Art Unit 2881
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